Hybrid Simulation of a Variable Transport Lag

SIMULATION ◽  
1969 ◽  
Vol 12 (2) ◽  
pp. 65-70
Author(s):  
R.N. Nilsen

The object of this paper is to present a hybrid solution to the problem of simulating an ideal transport lag hav ing a variable time delay. The dynamic range over which the allowable time delay may be realized by this tech nique is limited on the low end by the sampling rate and execution time of the digital computer, and on the high end by the memory capacity of the digital computer. Experimental results using signals consisting of either sinusoidal waveforms or random noise are presented.

2021 ◽  
Vol 11 (15) ◽  
pp. 7169
Author(s):  
Mohamed Allouche ◽  
Tarek Frikha ◽  
Mihai Mitrea ◽  
Gérard Memmi ◽  
Faten Chaabane

To bridge the current gap between the Blockchain expectancies and their intensive computation constraints, the present paper advances a lightweight processing solution, based on a load-balancing architecture, compatible with the lightweight/embedding processing paradigms. In this way, the execution of complex operations is securely delegated to an off-chain general-purpose computing machine while the intimate Blockchain operations are kept on-chain. The illustrations correspond to an on-chain Tezos configuration and to a multiprocessor ARM embedded platform (integrated into a Raspberry Pi). The performances are assessed in terms of security, execution time, and CPU consumption when achieving a visual document fingerprint task. It is thus demonstrated that the advanced solution makes it possible for a computing intensive application to be deployed under severely constrained computation and memory resources, as set by a Raspberry Pi 3. The experimental results show that up to nine Tezos nodes can be deployed on a single Raspberry Pi 3 and that the limitation is not derived from the memory but from the computation resources. The execution time with a limited number of fingerprints is 40% higher than using a classical PC solution (value computed with 95% relative error lower than 5%).


Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 1201
Author(s):  
Daniel dos Santos Mota ◽  
Elisabetta Tedeschi

The Conservative Power Theory (CPT) emerged in recent decades as a theoretical framework for coping with harmonically distorted and unbalanced electric networks of ac power systems with a high participation of converter interfaced loads and generation. The CPT measurements are intrinsically linked to moving averages (MA) over one period of the grid. If the CPT is to be used in a low-inertia isolated-grid scenario, which is subjected to frequency variations, adaptive moving averages (AMA) are necessary. This paper reviews an efficient way of computing MAs and turns it into an adaptive one. It shows that an easily available variable time delay block, from MATLAB, causes steady-state errors in the measurements when the grid frequency varies. A new variable time delay block is, thus, proposed. Nonetheless, natural pulsations in the instantaneous power slip through MAs when the discrete moving average window does not fit perfectly the continuously varying period of the grid. A method consisting of weighing two MAs is reviewed and a new and effective hybrid AMA is proposed. The CPT transducers with the different choices of AMAs are compared via computer simulations of a single-phase voltage source feeding either a linear or a nonlinear load.


Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.


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