VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs

On-chip sensors, built using reconfigurable logic resources in field programmable gate arrays (FPGAs), have been shown to sense variations in signalpropagation delay, supply voltage and power consumption. These sensors have been successfully used to deploy security attacks called Remote Power Analysis (RPA) Attacks on FPGAs. The sensors proposed thus far consume significant logic resources and some of them could be used to deploy power viruses. In this paper, a sensor (named VITI) occupying a far smaller footprint than existing sensors is presented. VITI is a self-calibrating on-chip sensor design, constructed using adjustable delay elements, flip-flops and LUT elements instead of combinational loops, bulky carry chains or latches. Self-calibration enables VITI the autonomous adaptation to differing situations (such as increased power consumption, temperature changes or placement of the sensor in faraway locations from the circuit under attack). The efficacy of VITI for power consumption measurement was evaluated using Remote Power Analysis (RPA) attacks and results demonstrate recovery of a full 128-bit Advanced Encryption Standard (AES) key with only 20,000 power traces. Experiments demonstrate that VITI consumes 1/4th and 1/16th of the area compared to state-of-the-art sensors such as time to digital converters and ring oscillators for similar effectiveness.

Area efficient folded undecimator based ECG detector

This paper presents an area-efficient folded wavelet filter-based Electrocardiogram (ECG) detector for cardiac pacemakers. The modified folded undecimator based detector consists of Wavelet Filter Bank, QRS complex detector with Generalized Likelihood Ratio Test (GLRT) block and noise detector. A high-level transformation technique such as folding transformation and Cutset retiming are applied to the GLRT block in order to reduce the silicon area. Folding is a high-level transformation applied at the architectural level to enhance the performance of DSP architectures. It reduces the number of adders, multipliers and delay elements in the architecture. The Cutset retiming reduces clock period of the architecture by changing position of delay elements in the critical path. The folding transformation and cutset retiming implement the functional blocks of the GLRT circuit with minimum hardware. The modified folded ECG detector is tested for short term and long-term MIT-BIH databases. The results show that the modified folded undecimator detector has hardware savings and achieves sensitivity of 99.95%, positive prediction of 99.97% and Detection Error Rate (DER) of 0.061. The folded GLRT block architecture is synthesized with FPGA Zed board XC7Z010CLG484-1. Results show that the device utilization and power consumption are lesser than the conventional GLRT structure.

The Dynamics of Continuous Control Systems with Delay Elements as Part of Correction Filters

Matters concerned with the application of correction devices containing delay elements are addressed. Such filters are proposed as an alternative to the high-pass filters and low-pass first-order filters that are widely used in control systems. It is shown that by using filters containing delay elements, the power of high-frequency interference in the controller output signal can be reduced by up to 30% in comparison with the conventional filters. It should be noted that these results are obtained in using the proposed filters in closed-loop continuous systems. Two filter configuration versions used in control applications were analyzed. In the first version, the filters are connected in series in the control loop (as applied to astatic systems with a proportional-differentiating controller in both linear and relay modes of operation). In the second version, a correction filter connected in the local feedback is used (taking a generalized representation of the instrument-assisted position tracking system as an example). The article proposes a fairly simple method for determining the parameters of filters with a delay element that make it possible to use conventional techniques for synthesizing controllers in the frequency domain and estimating their dynamic properties.

Termite pyrotechnic compositions of iron and alkaline earth metals peroxides

The fallowing article presents the combustion studies of Fe/alkaline earth metals peroxides composition. It contains a literature review and the results of own research, which aim is to determine the possibility of using iron-based thermite compositions in time delay elements. The article focuses on the investigation of combustion front propagation rate as a function of a pressing load, the iron content and the purity of used oxidants. The DSC, TG and XRD analysis confirmed that reactions in this system occurs mainly in the solid state.

Wideband Beam Steering Concept for Terahertz Time-Domain Spectroscopy: Theoretical Considerations

Photonic true time delay beam steering on the transmitter side of terahertz time-domain spectroscopy (THz TDS) systems requires many wideband variable optical delay elements and an array of coherently driven emitters operating over a huge bandwidth. We propose driving the THz TDS system with a monolithic mode-locked laser diode (MLLD). This allows us to use integrated optical ring resonators (ORRs) whose periodic group delay spectra are aligned with the spectrum of the MLLD as variable optical delay elements. We show by simulation that a tuning range equal to one round-trip time of the MLLD is sufficient for beam steering to any elevation angle and that the loss introduced by the ORR is less than 0.1 dB. We find that the free spectral ranges (FSRs) of the ORR and the MLLD need to be matched to 0.01% so that the pulse is not significantly broadened by third-order dispersion. Furthermore, the MLLD needs to be frequency-stabilized to about 100 MHz to prevent significant phase errors in the terahertz signal. We compare different element distributions for the array and show that a distribution according to a Golomb ruler offers both reasonable directivity and no grating lobes from 50 GHz to 1 THz.

Area-Efficient Pipelined FFT Processor for Zero-Padded Signals

This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors.