Residue code based low cost SEU-tolerant fir filter design for OBP satellite communication systems

Future wireless communication systems are facing with many challenges due to their complexity and diversification. Orthogonal frequency division multiplexing (OFDM) in 4G cannot meet the requirements in future scenarios, thus alternative multicarrier modulation (MCM) candidates for future physical layer have been extensively studied in the academic field, for example, filter bank multicarrier (FBMC), generalized frequency division multiplexing (GFDM), universal filtered multicarrier (UFMC), filtered OFDM (F-OFDM), and so forth, wherein the prototype filter design is an essential component based on which the synthesis and analysis filters are derived. This paper presents a comprehensive survey on the recent advances of finite impulse response (FIR) filter design methods in MCM based communication systems. Firstly, the fundamental aspects are examined, including the introduction of existing waveform candidates and the principle of FIR filter design. Then the methods of FIR filter design are summarized in details and we focus on the following three categories—frequency sampling methods, windowing based methods and optimization based methods. Finally, the performances of various FIR design methods are evaluated and quantified by power spectral density (PSD) and bit error rate (BER), and different MCM schemes as well as their potential prototype filters are discussed.

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Low-Cost Design of an FIR Filter by Using a Coefficient Mapping Method

Mathematical Problems in Engineering ◽

10.1155/2013/495207 ◽

2013 ◽

Vol 2013 ◽

pp. 1-6

Author(s):

Ming-Chih Chen ◽

Hong-Yi Wu

Keyword(s):

Filter Design ◽

Finite Impulse Response ◽

Critical Path ◽

Low Cost ◽

Fir Filter ◽

Mapping Method ◽

Path Delay ◽

Filter Performance ◽

Code Division Multiple ◽

Fir Filter Design

This work presents a novel coefficient mapping method to reduce the area cost of the finite impulse response (FIR) filter design, especially for optimizing its coefficients. Being capable of reducing the area cost and improving the filter performance, the proposed mapping method consists of four steps: quantization of coefficients, import of parameters, constitution of prime coefficients with parameters, and constitution of residual coefficients with prime coefficients. Effectiveness of the proposed coefficient mapping method is verified by selecting the 48-tap filter of IS-95 code division multiple access (CDMA) standard as the benchmark. Experimental results indicate that the proposed design with canonical signed digit (CSD) coefficients can operate at 86 MHz with an area of 241,813 um2, leading to a throughput rate of 1,382 Mbps. Its ratio of throughput/area is 5,715 Kbps/um2, yielding a higher performance than that of previous designs. In summary, the proposed design reduces 5.7% of the total filter area, shortens 25.7% of the critical path delay, and improves 14.8% of the throughput/area by a value over that of the best design reported before.

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High Speed FIR Filter Design using Multiplier Sharing and Sub-Expression Elimination Method

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.d5310.118419 ◽

2019 ◽

Vol 8 (4) ◽

pp. 7414-7417

Keyword(s):

High Speed ◽

Simple Structure ◽

Filter Design ◽

Low Cost ◽

Fir Filter ◽

Access Time ◽

Chip Area ◽

Filter Order ◽

The Cost ◽

Fir Filter Design

FIR filter is the basic filter used in many DSP applications because of its linear phase , stability , low cost and simple structure . Designing a high- speed and hardware efficient FIR filter is a very difficult task as the complexity increases with the filter order .In most Application the higher order filters are required but the memory usage of filter increases exponentially with the order of the filter using multipliers occupy a large chip area and need more access time. So the design and implementation of highly efficient look up table (LUT) based circuit for the implementation using DA Algorithm increases the speed. Multiplier sharing and sub-expression elimination methods are proposed to optimize the Structural adders. These methods split the structural adders into smaller adder blocks to reduce the delay. In order to reduce the complexity of structural adders round-off can be performed at the cost of sacrificing precision of the filter.

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