Phase shifter and broadband XOR logic gate based on edge-mode–type spin wave in the waveguide

2021 ◽  
Vol 134 (3) ◽  
pp. 37003
Author(s):  
Lei Zheng ◽  
Dainan Zhang ◽  
Lichuan Jin ◽  
Tianlong Wen ◽  
Yulong Liao ◽  
...  
Keyword(s):  
Spin Wave ◽  
Phase Shifter ◽  
Logic Gate ◽  
Edge Mode

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

A reconfigurable scheme for realization of electro-optical logic gate based on silicon-graphene Mach–Zhender interferometer

2019 ◽  
Vol 33 (04) ◽  
pp. 1950005
Author(s):  
Hossein Zivarian ◽  
Abbas Zarifkar
Keyword(s):  
High Speed ◽  
High Performance ◽  
Phase Shifter ◽  
Logic Gate ◽  
Extinction Ratio ◽  
Slot Waveguide ◽  
Optical Logic ◽  
Eye Diagram ◽  
Optical Logic Gate ◽  
Operational Modes

In this paper, we propose a reconfigurable scheme for implementation of an electro-optical logic gate by utilizing a Mach–Zehnder interferometer (MZI)-based structure. In order to achieve high performance and small footprint for the proposed logic gate, we have used a compact, broadband, low power and high speed MZI-based electro-optical switch which consists of a silicon-graphene slot waveguide as phase shifter in each arm of the MZI structure. Our design can perform electro-optical AND, OR and XOR logic functions in three different operational modes by using three electrical control signals. The functionality of the reconfigurable electro-optical logic gate is investigated with the help of eye diagram analysis for all three operational modes. Simulation results show that the proposed reconfigurable logic gate is able to work under at least 62.5 Gbit/s with high extinction ratio (ER) about 24.6 dB for transverse electric polarization mode at telecommunication wavelength of 1.55 [Formula: see text]m.

Logic Devices with Spin Wave Buses - an Approach to Scalable Magneto-Electric Circuitry

2008 ◽  
Vol 1067 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Yina Wu ◽  
Ji-Young Kim ◽  
Augustin Hong ◽  
...  
Keyword(s):  
Spin Wave ◽  
Room Temperature ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Logic Device ◽  
Logic Devices ◽  
Magnetic Circuits ◽  
Micrometer Scale ◽  
Magnetization Signal

ABSTRACTWe analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1μm2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

scholarly journals Nanoscale spin wave valve and phase shifter

2012 ◽  
Vol 100 (17) ◽  
pp. 172408 ◽  
Author(s):  
Y. Au ◽  
M. Dvornik ◽  
O. Dmytriiev ◽  
V. V. Kruglyak
Keyword(s):  
Spin Wave ◽  
Phase Shifter

A Multioctave Edge Mode Non Reciprocal Phase Shifter

1977 ◽  
Author(s):  
L. Courtois ◽  
G. Forterre ◽  
J. Marcoux
Keyword(s):  
Phase Shifter ◽  
Edge Mode

scholarly journals 2-output Spin Wave Programmable Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Spin Wave ◽  
Boolean Functions ◽  
State Of The Art ◽  
Logic Gate ◽  
Object Oriented ◽  
Programmable Logic ◽  
Area Reduction ◽  
Gate Structure ◽  
Cmos Implementation ◽  
Practical Implications

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing \{AND, OR, NAND, NOR\} and \{XOR and XNOR\} functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

scholarly journals 4-output Programmable Spin Wave Logic Gate

2020 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
Logic Gate

scholarly journals 4-output Programmable Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Boolean Function ◽  
Spin Wave ◽  
Logic Gate ◽  
Logic Gates ◽  
Data Representation ◽  
Output Energy ◽  
Element Subset ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

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