Logic Devices with Spin Wave Buses - an Approach to Scalable Magneto-Electric Circuitry

2008 ◽  
Vol 1067 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Yina Wu ◽  
Ji-Young Kim ◽  
Augustin Hong ◽  
...  
Keyword(s):  
Spin Wave ◽  
Room Temperature ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Logic Device ◽  
Logic Devices ◽  
Magnetic Circuits ◽  
Micrometer Scale ◽  
Magnetization Signal

ABSTRACTWe analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1μm2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

Spin Wave Based Logic Circuits

2007 ◽  
Vol 998 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Joo-Young Lee ◽  
Kang Wang ◽  
Dok Won Lee ◽  
...  
Keyword(s):  
Magnetic Field ◽  
External Magnetic Field ◽  
Spin Wave ◽  
Room Temperature ◽  
Ferromagnetic Film ◽  
Logic Gates ◽  
Logic Circuits ◽  
Device Structure ◽  
Wave Transport ◽  
Ferromagnetic Nanostructures

ABSTRACTWe investigate spin wave propagation and interference in conducting ferromagnetic nanostructures for potential application in spin wave based logic circuits. The novelty of this approach is that information transmission is accomplished without charge transfer. A bit of information is encoded into the phase of spin wave propagating in a nanometer thick ferromagnetic film. A set of “AND”, “NOR”, and “NOT” logic gates can be realized in one device structure by utilizing the effect of spin wave superposition. We present experimental data on spin wave transport in 100nm CoFe films at room temperature obtained by the propagation spin wave spectroscopy technique. Spin wave transport has been studied in the frequency range from 0.5 GHz to 6.0 GHz under different configurations of the external magnetic field. Both phase and amplitude of the spin wave signal are sensitive to the external magnetic field showing 60Deg/10G and 4dB/20G modulation rates, respectively. Potentially, spin wave based logic circuits may compete with traditional electron-based ones in terms of logic functionality and power consumption. The shortcomings of the spin wave based circuits are discussed.

Programmable Logic Gates Based on Tunable Multistable Mechanisms

2019 ◽  
Author(s):  
Mohamed Zanaty ◽  
Hubert Schneegans ◽  
Ilan Vardi ◽  
Simon Henein
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Building Blocks ◽  
Programmable Logic ◽  
Logic Device ◽  
Logic Function ◽  
Element Analysis ◽  
Stability Behavior ◽  
Binary Logic ◽  
Logical Operations

Abstract Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on modifiable boundary conditions as defined and analyzed in our previous work. The logical state of a PMM is defined by its stability and logical operations are implemented by modifying the stability behavior of the mechanism. Our programmable logic device has two qualitatively different sets of inputs. The first set determines the logic function to be computed. The second set represents the logical inputs. The output is a single logical value, “true” if the mechanism changes state and “false” otherwise. In this way, we are able to mechanically implement a set of binary logical operations. This implementation is validated using an analytical model characterizing the qualitative stability behavior of the mechanism. This was further verified using finite element analysis and experimental demonstration.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals Exploring the design space of recombinase logic circuits.

2019 ◽  
Author(s):  
Sarah Guiziou ◽  
Guillaume Perution-Kihli ◽  
Federico Ulliana ◽  
Michel Leclere ◽  
Jerome Bonnet
Keyword(s):  
Design Space ◽  
Scale Up ◽  
Single Layer ◽  
Logic Gates ◽  
Regulatory Elements ◽  
Logic Circuits ◽  
Logic Function ◽  
Dna Inversion ◽  
Logic Devices ◽  
Logic Functions

Logic circuits operating in living cells are generally built by mimicking electronic layouts, and scale-up is accomplished using additional layers of elementary logic gates like NOT and NOR gates. Recombinase-based logic, in which logic is implemented using DNA inversion or excision, allows for highly efficient, compact and single-layer design architectures. However, recombinase logic architectures depart from electronic design principles, and gate design performed empirically is challenging for an increasing number of inputs. Here we used a combinatorial approach to explore the design space of recombinase logic devices. We generated combinations and permutations of recombination sites, genes, and regulatory elements, for a total of ~19 million designs supporting the implementation of all 2- and 3-input logic functions and up to 92% of 4-input logic functions. We estimated the influence of different design constraints on the number of executable functions, and found that the use of DNA inversion and transcriptional terminators were key factors to implement the vast majority of logic functions. We provide a user-friendly interface, called RECOMBINATOR (http://recombinator.lirmm.fr/index.php), that enable users to navigate the design space of recombinase-based logic, find architectures implementing a specific logic function and sort them according to various biological criteria. Finally, we define a set of 16 architectures from which all 256 3-input logic functions can be derived. This work provides a theoretical foundation for the systematic exploration and design of single-layer recombinase logic devices.

NMOS Logic Circuits Using 4H-SiC MOSFETs for High Temperature Applications

2010 ◽  
Vol 645-648 ◽  
pp. 1143-1146 ◽  
Author(s):  
Martin Le-Huu ◽  
Frederik F. Schrey ◽  
Michael Grieb ◽  
H. Schmitt ◽  
Volker Haeublein ◽  
...  
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Constant Voltage ◽  
Gate Operation ◽  
Operating Field ◽  
Voltage Stress ◽  
High Temperature Operation

Normally-off 4H-SiC MOSFETs are used to build NMOS logic gates intended for high temperature operation. The logic gates are characterized between 25°C and 500°C. Stable gate operation for more than 200h at 400°C in air is demonstrated. The excellent MOS reliability is quantified using I-V curves to dielectric breakdown and constant voltage stress to breakdown at 400°C. Although the effective tunneling barrier height B for electrons lowers to 2eV at 400°C, the extrapolated lifetime from constant voltage stress to breakdown measurements is longer than 105h at 400°C for typical logic gate operating field strength of 2MV/cm.

scholarly journals 4-output Programmable Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Boolean Function ◽  
Spin Wave ◽  
Logic Gate ◽  
Logic Gates ◽  
Data Representation ◽  
Output Energy ◽  
Element Subset ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

scholarly journals Fan-out enabled spin wave majority gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Spin Wave ◽  
State Of The Art ◽  
Logic Gate ◽  
Logic Circuits ◽  
Boolean Logic ◽  
Function Evaluation ◽  
Majority Gate ◽  
Logic Function ◽  
Micromagnetic Simulations ◽  
Majority Logic

By its very nature, Spin Wave (SW) interference provides intrinsic support for Majority logic function evaluation. Due to this and the fact that the 3-input Majority (MAJ3) gate and the Inverter constitute a universal Boolean logic gate set, different MAJ3 gate implementations have been proposed. However, they cannot be directly utilized for the construction of larger SW logic circuits as they lack a key cascading mechanism, i.e., fan-out capability. In this paper, we introduce a novel ladder-shaped SW MAJ3 gate design able to provide a maximum fan-out of 2 (FO2). The proper gate functionality is validated by means of micromagnetic simulations, which also demonstrate that the amplitude mismatch between the two outputs is negligible proving that an FO2 is properly achieved. Additionally, we evaluate the gate area and compare it with SW state-of-the-art and 15nm CMOS counterparts working under the same conditions. Our results indicate that the proposed structure requires 12x less area than the 15 nm CMOS MAJ3 gate and that at the gate level the fan-out capability results in 16% area savings, when compared with the state-of-the-art SW majority gate counterparts.

scholarly journals GERBANG LOGIKA BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)

2009 ◽  
Vol 1 (1) ◽  
pp. 75-81
Author(s):  
Muhammad Irmansyah
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Logic Gate ◽  
Data Communication ◽  
Programmable Logic ◽  
Single Chip ◽  
Logic Device ◽  
Logic Devices ◽  
Programmable Logic Device ◽  
Programmable Logic Devices

In middle 1990, electronics industry had evolution in personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design basic logic gate AND, OR, NOT and combinational logic gate NAND and NOR.

scholarly journals 4-output Programmable Spin Wave Logic Gate

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Christoph Adelmann ◽  
Florin Ciubotaru ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Boolean Function ◽  
Spin Wave ◽  
Logic Gate ◽  
Logic Gates ◽  
Data Representation ◽  
Output Energy ◽  
Element Subset ◽  
Ultra Low Power ◽  
Computing Paradigm ◽  
Gate Structure

To bring Spin Wave (SW) based computing paradigm into practice and develop ultra low power Magnonic circuits and computation platforms, one needs basic logic gates that operate and can be cascaded within the SW domain without requiring back and forth conversion between the SW and voltage domains. To achieve this, SW gates have to possess intrinsic fanout capabilities, be input-output data representation coherent, and reconfigurable. In this paper, we address the first and the last requirements and propose a novel 4-output programmable SW logic. First, we introduce the gate structure and demonstrate that, by adjusting the gate output detection method, it can parallelly evaluate any 4-element subset of the 2-input Boolean function set AND, NAND, OR, NOR, XOR, and XNOR. Furthermore, we adjust the structure such that all its 4 outputs produce SWs with the same energy and demonstrate that it can evaluate Boolean function sets while providing fanout capabilities ranging from 1 to 4. We validate our approach by instantiating and simulating different gate configurations such as 4-output AND/OR, 4-output XOR/XNOR, output energy balanced 4-output AND/OR, and output energy balanced 4-output XOR/XNOR by means of Object Oriented Micromagnetic Framework (OOMMF) simulations. Finally, we evaluate the performance of our proposal in terms of delay and energy consumption and compare it against existing state-of-the-art SW and 16nm CMOS counterparts. The results indicate that for the same functionality, our approach provides 3x and 16x energy reduction, when compared with conventional SW and 16nm CMOS implementations, respectively.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

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