scholarly journals An Improved Multiplication Algorithm

2018 ◽  
Vol 7 (4.10) ◽  
pp. 1027
Author(s):  
S. Subha ◽  
. .
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Multiplication Algorithm

Multiplication is commonly used arithmetic operation in computers. An algorithm is proposed to perform multiplication of positive numbers using law of indices. The two inputs  A and B are represented as binary numbers. Iteratively, the number A is multiplied with the bits in B. The coefficients of the partial products are accumulated. These coefficients are represented as binary numbers, the result coefficients are calculated. The proposed algorithm is simulated using Quartus 2 tool for two four bit inputs. An improvement in timing by 18%  with comparable power consumption and increased area is observed for input of four bits. The proposed algorithm can be extended for n-bit inputs.   

scholarly journals A Multiplication Algorithm

2020 ◽  
Vol 9 (4) ◽  
pp. 3236-3237
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Partial Product ◽  
Multiplication Algorithm ◽  
Multiplication Process

Paper Setup must be in A4 size with Margin: Top 0.7”, Bottom 0.7”, Left 0.65”, 0.65”, Gutter 0”, and Gutter Position Top. Pap Abstract: Multiplication is common arithmetic operation in ALU. Many algorithm are proposed for multiplying two unsigned numbers in literature. This paper proposes algorithm to multiply two unsigned binary numbers of any size. The most significant two bits are used to determine the partial product by bit inspection. The rest of partial products are obtained by suitably shifting the previous partial products and adding the terms involving remainders. The remainder is obtained by taking one bit at a time from the MSB-2 position assuming numbers are indexed from zero in LSB to maximum-1 in MSB. The multiplication process is performed as series of additions, shifts in this method. The proposed method is simulated in Quartus2 Toolkit. It is compared to the in-built multiplication process of the tool. A timing improvement of 9.5% with comparable power consumption is obtained with same pin count.

Bit Forwarding 3-Bits Technique for Efficient Modular Exponentiation

2017 ◽  
Vol 11 (2) ◽  
pp. 11-24
Author(s):  
Satyanarayana Vollala ◽  
B. Shameedha Begum ◽  
Amit D. Joshi ◽  
N. Ramasubramanian
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Efficient Implementation ◽  
Public Key ◽  
Modular Exponentiation ◽  
Modular Multiplication ◽  
The Public ◽  
Public Key Cryptosystems ◽  
Security Services ◽  
The Cost

It is widely recognized that the public-key cryptosystems are playing tremendously an important role for providing the security services. In majority of the cryptosystems the crucial arithmetic operation is modular exponentiation. It is composed of a series of modular multiplications. Hence, the performance of any cryptosystem is strongly depends on the efficient implementation of these operations. This paper presents the Bit Forwarding 3-bits(BFW3) technique for efficient implementation of modular exponentiation. The modular multiplication involved in BFW3 is evaluated with the help of Montgomery method. These techniques improves the performance by reducing the frequency of modular multiplications. Results shows that the BFW3 technique is able to reduce the frequency of multiplications by 18.20% for 1024-bit exponent. This reduction resulted in increased throughput of 18.11% in comparison with MME42_C2 at the cost of 1.09% extra area. The power consumption reduced by 8.53% thereby saving the energy up to 10.10%.

scholarly journals Design and Evaluation of a 32-bit Carry Select Adder using 4-bit Hybrid CLA Adder

2021 ◽  
Vol 20 (2) ◽  
pp. 1-7
Author(s):  
Muhammad Saddam Hossain ◽  
Farhadur Arifin
Keyword(s):  
Power Consumption ◽  
Design Methodology ◽  
Arithmetic Operation ◽  
Logic Circuits ◽  
Hybrid Logic ◽  
Basic Unit ◽  
Improve Performance ◽  
Look Ahead ◽  
Carry Select Adder ◽  
Critical Paths

Adder circuits play a remarkable role in modern microprocessor. Adders are widely used in critical paths of arithmetic operation such as multiplication and subtraction. A Carry Select Adder (CSA) design methodology using a modified 4-bit Carry Look-Ahead (CLA) Adder has been proposed in this research. The proposed 4-bit CLA used hybrid logic style based logic circuits for Carry Generate (Gi) and Carry Propagate (Pi) functions in order to improve performance and reduce the number of transistor used. The modified 4-bit CLA is used as the basic unit for implementation of 32-bit CSA. The proposed design of hybrid CLA based 32-bit CSA has been compared with conventional static CMOS based 32-bit CSA and 32-bit Ripple Cary Adder (RCA) by conducting simulation using Cadence Virtuoso. Power consumption and delay in the proposed 32-bit CSA found 322.6 (uW) and 0.556 (ns) whereas power and delay in the conventional 32-bit CSA was 455.4 (uW) and 0.667 (ns) respectively. We have done all the simulation using Cadence Virtuoso 90 nm tool.

scholarly journals Implementation of High Speed Low Power Systolic Multiplier Based on Irreducible Trinomials

2020 ◽  
Vol 8 (5) ◽  
pp. 223-225
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Functional Verification ◽  
Multiplication Algorithm ◽  
Systolic Multiplier

This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.

Compositional Tuning of Negative Differential Resistance in Bulk Silver Iodide Memristor

2020 ◽  
Author(s):  
SMITA GAJANAN NAIK ◽  
Mohammad Hussain Kasim Rabinal
Keyword(s):  
Power Consumption ◽  
Negative Differential Resistance ◽  
Silver Iodide ◽  
Differential Resistance ◽  
Fast Response ◽  
Low Power Consumption ◽  
Switching Effect ◽  
Memory Switching ◽  
Bulk Silver ◽  
Emerging Memory

Electrical memory switching effect has received a great interest to develop emerging memory technology such as memristors. The high density, fast response, multi-bit storage and low power consumption are their...

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

Analysis of Characteristics of Halogen and LED Automobile Lamps

2020 ◽  
pp. 57-62
Author(s):  
Olga Yu. Kovalenko ◽  
Yulia A. Zhuravlyova
Keyword(s):  
Power Consumption ◽  
Flip Chip ◽  
Weather Conditions ◽  
Luminous Flux ◽  
Luminous Efficacy ◽  
Colour Temperature ◽  
Study Results ◽  
Calculation Results ◽  
Mandatory Rules ◽  
Halogen Lamps

This work contains analysis of characteristics of automobile lamps by Philips, KOITO, ETI flip chip LEDs, Osram, General Electric (GE), Gtinthebox, OSLAMPledbulbs with H1, H4, H7, H11 caps: luminous flux, luminous efficacy, correlated colour temperature. Characteristics of the studied samples are analysed before the operation of the lamps. The analysis of the calculation results allows us to make a conclusion that the values of correlated colour temperature of halogen lamps are close to the parameters declared by manufacturers. The analysis of the study results has shown that, based on actual values of correlated colour temperature, it is not advisable to use LED lamps in unfavourable weather conditions (such as rain, fog, snow). The results of the study demonstrate that there is a slight dispersion of actual values of luminous flux of halogen lamps by different manufacturers. Maximum variation between values of luminous flux of different lamps does not exceed 14 %. The analysis of the measurement results has shown that actual values of luminous flux of all halogen lamps comply with the mandatory rules specified in the UN/ECE Regulation No. 37 and luminous flux of LED lamps exceeds maximum allowable value by more than 8 %. Luminous efficacy of LED lamps is higher than that of halogen lamps: more than 82 lm/W and lower power consumption. The results of the measurements have shown that power consumption of a LED automobile lamp is lower than that of similar halogen lamps by 3 times and their luminous efficacy is higher by 5 times.

ESTIMATION OF POWER CONSUMPTION DISTRIBUTION IN FPGA-PROJECTS

2014 ◽  
pp. 192-196
Author(s):  
A. Drozd ◽  
◽  
S. Mileiko ◽  
V. Kalinichenko ◽  
N. Ulchenko
Keyword(s):  
Power Consumption
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