scholarly journals A Multiplication Algorithm

2020 ◽  
Vol 9 (4) ◽  
pp. 3236-3237
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Partial Product ◽  
Multiplication Algorithm ◽  
Multiplication Process

Paper Setup must be in A4 size with Margin: Top 0.7”, Bottom 0.7”, Left 0.65”, 0.65”, Gutter 0”, and Gutter Position Top. Pap Abstract: Multiplication is common arithmetic operation in ALU. Many algorithm are proposed for multiplying two unsigned numbers in literature. This paper proposes algorithm to multiply two unsigned binary numbers of any size. The most significant two bits are used to determine the partial product by bit inspection. The rest of partial products are obtained by suitably shifting the previous partial products and adding the terms involving remainders. The remainder is obtained by taking one bit at a time from the MSB-2 position assuming numbers are indexed from zero in LSB to maximum-1 in MSB. The multiplication process is performed as series of additions, shifts in this method. The proposed method is simulated in Quartus2 Toolkit. It is compared to the in-built multiplication process of the tool. A timing improvement of 9.5% with comparable power consumption is obtained with same pin count.

scholarly journals An Improved Multiplication Algorithm

2018 ◽  
Vol 7 (4.10) ◽  
pp. 1027
Author(s):  
S. Subha ◽  
. .
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Multiplication Algorithm

Multiplication is commonly used arithmetic operation in computers. An algorithm is proposed to perform multiplication of positive numbers using law of indices. The two inputs  A and B are represented as binary numbers. Iteratively, the number A is multiplied with the bits in B. The coefficients of the partial products are accumulated. These coefficients are represented as binary numbers, the result coefficients are calculated. The proposed algorithm is simulated using Quartus 2 tool for two four bit inputs. An improvement in timing by 18%  with comparable power consumption and increased area is observed for input of four bits. The proposed algorithm can be extended for n-bit inputs.   

Design and Implementation of Modified Partial Product Reduction Tree for High Speed Multiplication

2013 ◽  
Vol 2 (1) ◽  
pp. 15
Author(s):  
Sachin B. Jadhav ◽  
Jayamala K. Patil ◽  
Ramesh T. Patil
Keyword(s):  
Binary Tree ◽  
High Speed ◽  
Hardware Implementation ◽  
Critical Path ◽  
Partial Product ◽  
Design And Implementation ◽  
Multiplication Operation ◽  
Multiplication Process ◽  
Major Bottleneck ◽  
Speed Up

This paper presents the details of hardware implementation of modified partial product reduction tree using 4:2 and 5:2 compressors. Speed of multiplication operation is improved by using higher compressors .In order to improve the speed of the multiplication process within the computational unit; there is a major bottleneck that is needed to be considered that is the partial products reduction network which is used in the multiplication block. For implementation of this stage require addition of large operands that involve long paths for carry propagation. The proposed architecture is based on binary tree constructed using modified 4:2 and 5:2 compressor circuits. Increasing the speed of operation is achieved by using higher modified compressors in critical path. Our objective of work is, to increase the speed of multiplication operation by minimizing the number of combinational gates using higher n:2 compressors. The experimental test of the proposed modified compressor is done using Spartan-3FPGA device (XC3S400 PQ-208). Using tree architectures for the partial products reduction network represent an attractive solution that is frequently applied to speed up the multiplication process. The simulation result shows 4:2 and 5:2 compressor output which is done using Questa Sim 6.4c Mentor Graphics tool.

scholarly journals Design and Analysis of a Low Power Binary Counter-based Approximate Multiplier Architecture

2019 ◽  
Vol 8 (9) ◽  
pp. 1028-1033
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Energy Efficient ◽  
Arithmetic Operation ◽  
Partial Product ◽  
Approximation Techniques ◽  
Fundamental Building Block ◽  
Binary Counter ◽  
Counter Circuit ◽  
Product Accumulation

Multiplication has become the fundamental arithmetic operation in modern electronic world. Many researches in Signal processing and image processing applications are looking for energy efficient architectures. These applications exhibit error tolerance thus laying foundation for approximation techniques. The proposed work utilizes a new binary counter for partial product accumulation in a segmentation based approximate multiplication technique. The fundamental building block of the counter is a 3-bit stack circuit, which combines each of “Logic 1” bits collectively, after which a stacking process is done to convert two 3-bit modules into a 6-bit stack module. The counter circuit is obtained by converting the bit stacks to binary counts, without any XOR gates on the critical line of operation. This leads to design of binary counters with effective yield of power and delay. Moreover, applying these counters for partial product accumulation in the approximate multipliers found to be more effective when compared with conventional techniques. In future, these counter based approximate multipliers can be utilized to design energy efficient filters for image processing and signal processing applications.

scholarly journals CRBBE ALGORITHM FOR LOW POWER AND HIGH SPEED MULTIPLIER DESIGN

2014 ◽  
pp. 104-108
Author(s):  
K. SANJEEVARAO ◽  
A. RAMKUMAR
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Power Reduction ◽  
Partial Product ◽  
Large Area ◽  
Encoding Scheme ◽  
Long Latency ◽  
Vlsi Technology ◽  
High Radix ◽  
Digital Multipliers

With the advent of the VLSI technology, designers could design simple chips with the more number of transistors. multipliers have large area, long latency and consume considerable power. Reduction of power consumption makes a device reliable. and The use of redundant binary (RB) arithmetic in the design of high-speed digital multipliers is beneficial due to its high modularity and carry-free addition, a high-radix-modified booth encoding algorithm is desired. However its use is hampered by the complexity of generating the hard multiples and the overheads resulting from negative multiples and normal binary(NB) to RB conversion. This paper proposes new RB booth encoding scheme to circumvent these problems. The idea is to polarize two adjacent booth encoded digits to directly from an RB partial product to avoid the hard multiple of high-radix booth encoding without incurring any correction vector, and the algorithm achieved high speed compared to existing multiplication algorithms for a gamut of power –of-to word lengths up to 64 b.

scholarly journals Logic Design and Power Optimization of Floating-Point Multipliers

2022 ◽  
Vol 2022 ◽  
pp. 1-10
Author(s):  
Na Bai ◽  
Hang Li ◽  
Jiming Lv ◽  
Shuai Yang ◽  
Yaohua Xu
Keyword(s):  
Power Consumption ◽  
Power Optimization ◽  
Current Situation ◽  
Floating Point ◽  
Cell Process ◽  
Logic Design ◽  
Flowing Water ◽  
Partial Product ◽  
Standard Cell ◽  
Single Precision

Under IEEE-754 standard, for the current situation of excessive time and power consumption of multiplication operations in single-precision floating-point operations, the expanded boothwallace algorithm is used, and the partial product caused by booth coding is rounded and predicted with the symbolic expansion idea, and the partial product caused by single-precision floating-point multiplication and the accumulation of partial products are optimized, and the flowing water is used to improve the throughput. Based on this, a series of verification and synthesis simulations are performed using the SMIC-7 nm standard cell process. It is verified that the new single-precision floating-point multiplier can achieve a smaller power share compared to the conventional single-precision floating-point multiplier.

Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA

2016 ◽  
Vol 6 (3) ◽  
pp. 1205
Author(s):  
M. Bhavani ◽  
M. Siva Kumar ◽  
K. Srinivas Rao
Keyword(s):  
Power Consumption ◽  
Multiplication Process ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Ancient Mathematics ◽  
Better Than

<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.</p>

scholarly journals Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA

2016 ◽  
Vol 6 (3) ◽  
pp. 1205
Author(s):  
M. Bhavani ◽  
M. Siva Kumar ◽  
K. Srinivas Rao
Keyword(s):  
Power Consumption ◽  
Multiplication Process ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Ancient Mathematics ◽  
Better Than

<p>In any integrated chip compulsory adders are required because first they are fast and second are the less power consumption and delay. And at the same time multiplication process is also used in various applications. So as the speed of multiplier increases then the speed of processor also increases. And hence we are proposing the Vedic multiplier using these adders. Vedic multiplier is an ancient mathematics which uses mainly 16 sutras for its operation. In this project we are using “urdhva triyagbhyam” sutra to do our process. This paper proposes the Vedic multiplier using the adders ripple carry adder(RCA) and carry look ahead adder(CLA) and puts forward that CLA is better than RCA.The major parameters we are simulating here are number of slices and delay. The code is written by using Verilog and is implemented using Xilinx ISE Design Suite.</p>

Bit Forwarding 3-Bits Technique for Efficient Modular Exponentiation

2017 ◽  
Vol 11 (2) ◽  
pp. 11-24
Author(s):  
Satyanarayana Vollala ◽  
B. Shameedha Begum ◽  
Amit D. Joshi ◽  
N. Ramasubramanian
Keyword(s):  
Power Consumption ◽  
Arithmetic Operation ◽  
Efficient Implementation ◽  
Public Key ◽  
Modular Exponentiation ◽  
Modular Multiplication ◽  
The Public ◽  
Public Key Cryptosystems ◽  
Security Services ◽  
The Cost

It is widely recognized that the public-key cryptosystems are playing tremendously an important role for providing the security services. In majority of the cryptosystems the crucial arithmetic operation is modular exponentiation. It is composed of a series of modular multiplications. Hence, the performance of any cryptosystem is strongly depends on the efficient implementation of these operations. This paper presents the Bit Forwarding 3-bits(BFW3) technique for efficient implementation of modular exponentiation. The modular multiplication involved in BFW3 is evaluated with the help of Montgomery method. These techniques improves the performance by reducing the frequency of modular multiplications. Results shows that the BFW3 technique is able to reduce the frequency of multiplications by 18.20% for 1024-bit exponent. This reduction resulted in increased throughput of 18.11% in comparison with MME42_C2 at the cost of 1.09% extra area. The power consumption reduced by 8.53% thereby saving the energy up to 10.10%.

scholarly journals A Fast Multiplication Approach Using a Tree-Based Structure

2020 ◽  
Vol 6 (1) ◽  
pp. 20-26
Author(s):  
Md Solaiman Mia
Keyword(s):  
Comparative Study ◽  
Time Complexity ◽  
Integer Number ◽  
Partial Product ◽  
Science And Engineering ◽  
Worst Case ◽  
Running Time ◽  
Multiplication Algorithm ◽  
Fast Multiplication ◽  
The Comparative Study

This paper presents a technique for integer number multiplication using a tree-based structure. In the proposed method, both the generation of the partial products and the addition of partial products are completed in the tree structure. The proposed multiplication approach has been designed in two steps: Firstly, the partial products are generated in a tree-based structure using the fewest numbers of gates. Secondly, diagonal partial products additions have been done by the partial products residing in the diagonal partial product nodes to get a faster multiplication result, where two partial product nodes Pi , and Pk,l are diagonal only if |i - k| = |j - l|where  i and k are the multiplicand bits; and j and l are the multiplier bits. The comparative study shows that the proposed multiplication algorithm outperforms the existing techniques; e.g., the proposed 4 × 4 multiplication algorithm improves 50% on the worst case running time complexity over the best known existing ones. GUB JOURNAL OF SCIENCE AND ENGINEERING, Vol 6(1), Dec 2019 P 20-26

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