Assembly of Fine-Pitch Carbon Nanotube Bundles for Electrical Interconnect Applications

2007 ◽  
Vol 990 ◽  
Author(s):  
Lingbo Zhu ◽  
Dennis W Hess ◽  
ChingPing Wong
Keyword(s):  
Transfer Process ◽  
High Growth ◽  
Electrical Interconnects ◽  
Fine Pitch ◽  
Snpb Solder ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Nanotube Growth ◽  
Mechanical Bonding ◽  
Measured Resistivity

ABSTRACTCarbon nanotubes (CNTs) have been proposed as electrical interconnects, due to their excellent properties. However, the current nanotube growth techniques suffer from several drawbacks. One of the main challenges for applying CNTs to the circuitry is the high growth temperature (>600°C). Such temperatures are incompatible with microelectronic processes. The other issue is the poor adhesion between CNTs and the substrates, which will result in long term reliability issues and high contact resistance. To overcome these disadvantages, we have successfully demonstrated a methodology that we term “CNT transfer technology”. The distinctive CNT-transfer-technology features are separation of CNT growth and CNT device assembly at solder reflow temperature. In this paper, we combined our expertise in growth of well-aligned open-ended CNT bundles with the CNT transfer process to assemble CNT bundles for fine-pitch interconnects applications. To demonstrate the feasibility of transfer process to assemble the fine-pitch CNT bundles, the CNT bundles with diameter, aspect-ratio and pitch of 25 μm, 4, and 80 μm, respectively, were assembled on the copper substrates. The measured resistivity of the long CNTs is ∼2.3×10−4 Ω-cm. The CNT-solder alloy interfaces were observed by the SEM. The results indicated that molten SnPb solder form strong mechanical bonding with open-ended CNTs, suggesting the superior CNT/solder interfacial properties by solder reflow process.

Reliability Analysis of a Wearable Sensor Patch (WSP) to Monitor ECG Signals

2017 ◽  
Vol 2017 (1) ◽  
pp. 000194-000200 ◽  
Author(s):  
Varun Soman ◽  
Mark D. Poliks ◽  
James N. Turner ◽  
Mark Schadt ◽  
Michael Shay ◽  
...  
Keyword(s):  
Wearable Sensor ◽  
Flexible Sensors ◽  
Ecg Signals ◽  
Snpb Solder ◽  
Reflow Temperature ◽  
Device Reliability ◽  
Solder Reflow ◽  
Real World Applications ◽  
Multiple Devices ◽  
Cte Mismatch

Abstract Flexible Hybrid Electronic (FHE) devices interface flexible sensors and circuits with conventional rigid electronic components. This work reports preliminary results for the reliability aspects of a project aimed at fabricating a Wearable Sensor Patch (WSP) to monitor ECG signals. The device was fabricated by interfacing flexible electroplated Cu circuit lines and an ECG sensor on a Kapton® polyimide (PI) substrate with rigid electronics connected using SnPb solder (reflow temperature: 204 °C), making it a FHE device. Phase I of this project faced reliability issues as Cu circuit lines were susceptible to failure due to cracking near the front-end signal conditioning chip. This issue needed to be resolved in Phase II of the project to produce a robust device fit to be used in real world applications. The effect of changes in Cu trace thickness (2 and 6 μm) and Kapton® PI thickness (2 and 5 mil) on device robustness was tested. Effect of the use of low reflow temperature SnBi solder (reflow temperature: 175 °C) on device reliability was also tested. Multiple devices fabricated using different configurations of Cu trace and Kapton® PI thicknesses and either SnPb or SnBi solder were bend tested to single out the most robust configuration. Improved solder pad design for Cu traces at solder joint sites was also tested. It was observed that only devices with 6 μm thick Cu traces, 2 mil thick Kapton® and SnBi solder had no defects as a result of thermal cycling during fabrication. They also performed best during bend testing. Some of the factors contributing to robustness of this configuration might be lower CTE mismatch due to lower solder reflow temperature as well as greater strength under bending due to increased thickness. Improved solder pad design for Cu traces also improved device robustness considerably.

Wire Bonding Advances for Multi-Chip and System in Package Devices

2018 ◽  
Vol 2018 (1) ◽  
pp. 000583-000588 ◽  
Author(s):  
Hui Xu ◽  
Aashish Shah ◽  
Basil Milton ◽  
Ivy Qin
Keyword(s):  
Light Emitting Diodes ◽  
Low Cost ◽  
High Growth ◽  
Wire Bonding ◽  
High Yield ◽  
Ball Bond ◽  
Light Emitting ◽  
Yield Rate ◽  
Fine Pitch ◽  
20 Nm

Abstract Wire bonding continues to be the most commonly used interconnection technology due to its low cost, high yield rate, increased flexibility and improved reliability. Among wire bonded packages, the high growth areas include Multi-Chip modules and System in Package (SiP) applications. A type of wire bonding, Stand-Off-Stitch Bond (SSB), is widely used in Multi-chip, die-to-die, SiP and light-emitting diodes (LEDs). The SSB process starts with a flat-topped bump bonding on the substrate or die, followed by the formation of a new ball bond (1st bond). The stitch bond (2nd bond) of that wire is bonded on top of the initial bump. This paper focuses on key SSB process steps, by examining the main challenges and solutions of SSB applications. We demonstrate ultra-fine pitch SSB process capability with 0.6 mil Au wire using newly developed response-based processes for sub-20 nm node wafer technology.

Development of a stress compensation layer for thin pixel modules 3D assembly

2014 ◽  
Vol 2014 (1) ◽  
pp. 000787-000793 ◽  
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.

Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

2015 ◽  
Vol 12 (1) ◽  
pp. 29-36
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.

Enhanced Processability and Thermal Fatigue Reliability With Low Melting Point SnBi Solder Alloy LMPA-Q

2021 ◽  
Author(s):  
Bart Vandevelde ◽  
Chinmay Nawghane ◽  
Riet Labie ◽  
Ralph Lauwaert ◽  
Daniel Werkhoven
Keyword(s):  
Thermal Cycling ◽  
Thermal Fatigue ◽  
Fatigue Reliability ◽  
Solder Alloys ◽  
Fine Pitch ◽  
Reflow Temperature ◽  
Thermal Cycling Testing ◽  
Lower Temperature ◽  
Reliability Performance ◽  
Harsh Conditions

Abstract SnBi based solder alloys become an interesting alternative for standard SnAgCu as they can be used to solder components at much lower temperature. The typically 50°C lower solder reflow temperature is less damaging for PCB and components, and also prevents hot tear and head-in-pillow failures for large fine pitch BGA components. A reasonable concern for these low-melting temperature solders is the thermal cycling reliability performance, in particular for harsh conditions such as automotive products. In this work, thermal cycling testing and failure analysis have been performed on 9 × 9 mm size QFN components and large chip components (2010 and 2512) which are typically sensitive to thermal fatigue. The results are benchmarked to standard SAC alloy. Also the process advantages from the low temperature solder alloys are depicted in this paper. Finally, the effect of Pb contamination on this SnBi based solder is investigated.

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