Reliability Analysis of a Wearable Sensor Patch (WSP) to Monitor ECG Signals

Abstract Flexible Hybrid Electronic (FHE) devices interface flexible sensors and circuits with conventional rigid electronic components. This work reports preliminary results for the reliability aspects of a project aimed at fabricating a Wearable Sensor Patch (WSP) to monitor ECG signals. The device was fabricated by interfacing flexible electroplated Cu circuit lines and an ECG sensor on a Kapton® polyimide (PI) substrate with rigid electronics connected using SnPb solder (reflow temperature: 204 °C), making it a FHE device. Phase I of this project faced reliability issues as Cu circuit lines were susceptible to failure due to cracking near the front-end signal conditioning chip. This issue needed to be resolved in Phase II of the project to produce a robust device fit to be used in real world applications. The effect of changes in Cu trace thickness (2 and 6 μm) and Kapton® PI thickness (2 and 5 mil) on device robustness was tested. Effect of the use of low reflow temperature SnBi solder (reflow temperature: 175 °C) on device reliability was also tested. Multiple devices fabricated using different configurations of Cu trace and Kapton® PI thicknesses and either SnPb or SnBi solder were bend tested to single out the most robust configuration. Improved solder pad design for Cu traces at solder joint sites was also tested. It was observed that only devices with 6 μm thick Cu traces, 2 mil thick Kapton® and SnBi solder had no defects as a result of thermal cycling during fabrication. They also performed best during bend testing. Some of the factors contributing to robustness of this configuration might be lower CTE mismatch due to lower solder reflow temperature as well as greater strength under bending due to increased thickness. Improved solder pad design for Cu traces also improved device robustness considerably.

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Assembly of Fine-Pitch Carbon Nanotube Bundles for Electrical Interconnect Applications

MRS Proceedings ◽

10.1557/proc-0990-b10-01 ◽

2007 ◽

Vol 990 ◽

Cited By ~ 1

Author(s):

Lingbo Zhu ◽

Dennis W Hess ◽

ChingPing Wong

Keyword(s):

Transfer Process ◽

High Growth ◽

Electrical Interconnects ◽

Fine Pitch ◽

Snpb Solder ◽

Reflow Temperature ◽

Solder Reflow ◽

Nanotube Growth ◽

Mechanical Bonding ◽

Measured Resistivity

ABSTRACTCarbon nanotubes (CNTs) have been proposed as electrical interconnects, due to their excellent properties. However, the current nanotube growth techniques suffer from several drawbacks. One of the main challenges for applying CNTs to the circuitry is the high growth temperature (>600°C). Such temperatures are incompatible with microelectronic processes. The other issue is the poor adhesion between CNTs and the substrates, which will result in long term reliability issues and high contact resistance. To overcome these disadvantages, we have successfully demonstrated a methodology that we term “CNT transfer technology”. The distinctive CNT-transfer-technology features are separation of CNT growth and CNT device assembly at solder reflow temperature. In this paper, we combined our expertise in growth of well-aligned open-ended CNT bundles with the CNT transfer process to assemble CNT bundles for fine-pitch interconnects applications. To demonstrate the feasibility of transfer process to assemble the fine-pitch CNT bundles, the CNT bundles with diameter, aspect-ratio and pitch of 25 μm, 4, and 80 μm, respectively, were assembled on the copper substrates. The measured resistivity of the long CNTs is ∼2.3×10−4 Ω-cm. The CNT-solder alloy interfaces were observed by the SEM. The results indicated that molten SnPb solder form strong mechanical bonding with open-ended CNTs, suggesting the superior CNT/solder interfacial properties by solder reflow process.

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Automated P-Wave Quality Assessment for Wearable Sensors

Proceedings ◽

10.3390/ecsa-5-05743 ◽

2018 ◽

Vol 4 (1) ◽

pp. 13

Author(s):

Diogo Tecelão ◽

Peter Charlton

Keyword(s):

At Risk ◽

Quality Assessment ◽

Wearable Sensors ◽

P Wave ◽

Sensor Data ◽

Wearable Sensor ◽

High Quality ◽

P Waves ◽

Ecg Signals ◽

Wave Morphology

Hospital patients recovering from major cardiac surgery are at risk of paroxysmal atrial fibrillation (AF), an arrhythmia which can be life-threatening. Wearable sensors are routinely used for electrocardiogram (ECG) monitoring in patients at risk of AF, providing real-time AF detection. However, wearable sensors could have greater impact if used to identify the subtle changes in P-wave morphology which precede AF. This would allow prophylactic treatment to be administered, potentially preventing AF. However, ECG signals acquired by wearable sensors are susceptible to artefact, making it difficult to distinguish between physiological changes in P-wave morphology, and changes due to noise. The aim of this study was to design and assess the performance of a novel automated P-wave quality assessment tool to identify high-quality P-waves, for AF prediction. We designed a two-stage algorithm which uses P-wave template-matching to assess quality. Its performance was assessed using the AFPDB, a database of wearable sensor ECG signals acquired from both healthy subjects and patients susceptible to AF. The algorithm’s quality assessments of 97,989 P-waves were compared to manual annotations. The algorithm identified high-quality P-waves with high sensitivity (93%) and good specificity (82%), indicating that it may have utility for identifying high-quality P-waves in wearable sensor data. Measurements of P-wave morphology derived from high-quality P-waves could be used to predict AF, improving patient outcomes, and reducing healthcare costs. Further studies assessing the clinical utility of the presented tool are warranted for validation.

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Development of a stress compensation layer for thin pixel modules 3D assembly

International Symposium on Microelectronics ◽

10.4071/isom-thp13 ◽

2014 ◽

Vol 2014 (1) ◽

pp. 000787-000793 ◽

Cited By ~ 1

Author(s):

G. Pares ◽

T. McMullen ◽

S. Tomé ◽

L. Vignoud ◽

R. Bates ◽

...

Keyword(s):

Room Temperature ◽

Flip Chip ◽

Building Blocks ◽

Back Side ◽

Pixel Detector ◽

Front Side ◽

Radiation Length ◽

Reflow Temperature ◽

Solder Reflow ◽

Deposition Conditions

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.

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Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.454 ◽

2015 ◽

Vol 12 (1) ◽

pp. 29-36

Author(s):

G. Pares ◽

T. McMullen ◽

S. Tomé ◽

L. Vignoud ◽

R. Bates ◽

...

Keyword(s):

Room Temperature ◽

Flip Chip ◽

Building Blocks ◽

Back Side ◽

Pixel Detector ◽

Front Side ◽

Radiation Length ◽

Reflow Temperature ◽

Solder Reflow ◽

Deposition Conditions

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.

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Dynamic warpage simulation of molded PCB under reflow process

Circuit World ◽

10.1108/cw-02-2021-0061 ◽

2021 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Chun Hei Edmund Sek ◽

M.Z. Abdullah ◽

Kok Hwa Hwa Yu ◽

Shaw Fong Wong

Keyword(s):

Form Factor ◽

Product Development ◽

Coefficient Of Thermal Expansion ◽

Circuit Board ◽

Product Development Process ◽

Total Force ◽

Reflow Process ◽

Content Type ◽

Reflow Temperature ◽

Cte Mismatch

Purpose This study aims to simulate molded printed circuit board (PCB) warpage behavior under reflow temperature distribution. Simulation models are used to estimate dynamic warpage behavior for different form factor sizes. Design/methodology/approach This study analyzes warpage during the reflow process. The shadow moiré experiment methodology is used to collect data on the dynamic warpage performance of a model with a form factor of 10mm × 10mm × 1mm. The temperature profile with heating from 25°C to 300°C at intervals of 50°C is used, and the sample is made to undergo a cooling process until it reaches the room temperature. Subsequently, ANSYS static structural simulation is performed on similar form factor models to ascertain the accuracy of the simulation results. Findings Results show that the deformation and total force induced by coefficient of thermal expansion (CTE) mismatch are examined based on the warpage performance of models with different sizes, that is, 45mm × 45mm × 1mm and 45mm × 15mm × 1mm. Compared with the experimental data, the simulated modeling accuracy yields a less than 5% deviation in the dynamic warpage prediction at a reflow temperature of 300°C. Results also reveal that the larger the model, the larger the warpage changes under the reflow temperature. Research limitations/implications The simulated warpage is limited to the temperature and force induced by CTE mismatch between two materials. The form factor of the ball-grid array model is limited to only three different sizes. The model is assumed to be steady, isothermal and static. The simulation adopts homogenous materials, as it cannot accurately model nonhomogeneous multilayered composite materials. Practical implications This study can provide engineers and researchers with a profound understanding of molded PCB warpage, minimal resource utilization and the improved product development process. Social implications The accurate prediction of molded PCB warpage can enable efficient product development and reduce resources and production time, thereby creating a sustainable environment. Originality/value The literature review points out that warpage in various types of PCBs was successfully examined, and that considerable efforts were exerted to investigate warpage reduction in PCB modules. However, PCB warpage studies are limited to bare PCBs. To the best of the authors’ knowledge, the examination of warpage in a molded PCB designed with a molded compound cover, as depicted in Figure 3, is yet to be conducted. A molded compound provides strong lattice support for PCBs to prevent deformation during the reflow process, which is a topic of considerable interest and should be explored.

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