Effects of Mechanical Strain on the Electrical Performance of Amorphous Silicon Thin-Film Transistors with a New Gate Dielectric

2009 ◽  
Vol 1196 ◽  
Author(s):  
Katherine Wei Song ◽  
Lin Han ◽  
Sigurd Wagner ◽  
Prashant Mandlik
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Hybrid Material ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Compressive Strain ◽  
Mechanical Strain ◽  
Electrical Performance ◽  
Silicon Thin Film ◽  
Transfer Characteristics

AbstractThe stiff SiNx gate dielectric in conventional amorphous silicon thin film transistors (TFTs) limits their flexibility by brittle fracture when in tension. We report the effect on the overall flexibility of TFTs of replacing the brittle SiNx gate dielectric with a new, resilient SiO2-silicone hybrid material, which is deposited by plasma enhanced chemical vapor deposition. Individual TFTs on a 50μm-thick polyimide foil were bent to known radii, and measurement of transfer characteristics were made both during strain and after re-flattening. Compared with conventional TFTs made with SiNx, TFTs made with the new hybrid material demonstrated similar flexibility when strained in compression and significantly increased flexibility when strained in tension. Under bending to compressive strain, all TFTs tested delaminated from the substrate for compressive strains greater than 2%. Conventional a-Si:H/SiNx TFTs have been previously found to delaminate at a similar compressive strain. Under bending to tensile strain, the most flexible TFTs made with the new hybrid material that were tested after re-flattening did not exhibit significant changes in transfer characteristics up to strains of ∼2.5%. Conventional a-Si:H/SiNx TFTs have been found to remain functional for strains of up to 0.5%, a value only one-fifth of that for TFTs made with the new hybrid material.

Stability of Amorphous Silicon Thin Film Transistors under Prolonged High Compressive Strain

2007 ◽  
Vol 989 ◽  
Author(s):  
Jian-Zhang Chen ◽  
I-Chun Cheng ◽  
Sigurd Wagner ◽  
Warren Jackson ◽  
Craig Perlov ◽  
...  
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Compressive Strain ◽  
Mechanical Strain ◽  
Channel Length ◽  
Silicon Thin Film ◽  
Roll To Roll ◽  
Hydrogenated Amorphous ◽  
Current Drop

AbstractWe studied the effect of prolonged mechanical strain on the electrical characteristics of thin-film transistors of hydrogenated amorphous silicon made at a process temperature of 150°C on 51-μm thick Kapton polyimide foil substrates. Effects are observed only at very high compressive strain of 1.8%. Tensile strain up to fracture at 0.3% to 0.5% does not show any effect, nor does compressive strain substantially less than 1.8%. The TFTs were stressed for times up to 23 days by bending around a tube with axis perpendicular to the channel length, and were evaluated in the flattened state. The changes observed are small. The threshold voltage is increased, the “on” current and the field effect mobility remain essentially constant, and the subthreshold slope, “off” current and gate leakage current drop somewhat. Overall, the observed changes are small. We conclude that mechanical strain caused by roll-to-roll processing and permanent shaping will have negligible effects on TFT performance.

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 424 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

Low frequency noise in amorphous silicon thin film transistors with SiNx gate dielectric

2009 ◽  
Vol 105 (12) ◽  
pp. 124504 ◽  
Author(s):  
S. L. Rumyantsev ◽  
Sung Hun Jin ◽  
M. S. Shur ◽  
Mun-Soo Park
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Low Frequency ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Silicon Thin Film

Hot-Wire Deposited Amorphous Silicon Thin-Film Transistors

1996 ◽  
Vol 420 ◽  
Author(s):  
R. E. I. Schropp ◽  
K. F. Feenstra ◽  
C. H. M. Van Der Werf ◽  
J. Holleman ◽  
H. Meiling
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Current Crowding ◽  
Hot Wire ◽  
Saturation Regime ◽  
Silicon Thin Film ◽  
Order Of Magnitude

AbstractWe present the first thin film transistors (TFTs) incorporating a low hydrogen content (5 - 9 at.-%) amorphous silicon (a-Si:H) layer deposited by the Hot-Wire Chemical Vapor Deposition (HWCVD) technique. This demonstrates the possibility of utilizing this material in devices. The deposition rate by Hot-Wire CVD is an order of magnitude higher than by Plasma Enhanced CVD. The switching ratio for TFTs based on HWCVD a-Si:H is better than 5 orders of magnitude. The field-effect mobility as determined from the saturation regime of the transfer characteristics is still quite poor. The interface with the gate dielectric needs further optimization. Current crowding effects, however, could be completely eliminated by a H2 plasma treatment of the HW-deposited intrinsic layer. In contrast to the PECVD reference device, the HWCVD device appears to be almost unsensitive to bias voltage stressing. This shows that HW-deposited material might be an approach to much more stable devices.

Effects of Mechanical Strain on Amorphous Silicon Thin-Film Transistors

2002 ◽  
Vol 715 ◽  
Author(s):  
H. Gleskova ◽  
S. Wagner ◽  
W. Soboyejo ◽  
Z. Suo
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistors ◽  
Tensile Strain ◽  
Mechanical Strain ◽  
Positive Sign ◽  
Silicon Thin Film ◽  
Polyimide Foil

AbstractWe evaluated a-Si:H TFTs fabricated on polyimide foil under uniaxial compressive or tensile strain. The strain was induced by bending or stretching. All experiments confirmed that the on-current and hence the electron linear mobility depend on strain å as μ = μ0 (1 + 26·ε), where tensile strain has a positive sign. Upon the application of stress the mobility changes instantly and then remains unchanged in measurements up to 40 hours. In the majority of the TFTs the off-current and leakage current do not change. In tension, the TFTs fail mechanically at a strain of ∼ 3x10-2 but recover if the strain is released ‘immediately’.

Thin-Film Transistors on PET at 100°C

2002 ◽  
Vol 715 ◽  
Author(s):  
J.P. Conde ◽  
P. Alpuim ◽  
V. Chu
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Contact Layer ◽  
Processing Temperature ◽  
Silicon Thin Film ◽  
Glass Substrates ◽  
Hydrogen Dilution ◽  
Polyethylene Terephthalate Substrate

AbstractBottom-gate amorphous silicon thin-film transistors were fabricated on a polyethylene terephthalate substrate. The maximum processing temperature was 100°C. The transistor characteristics are comparable, although still inferior, to those of standard amorphous silicon transistors fabricated on glass substrates. To obtain these characteristics, an extended anneal the processing temperature was required. The devices were fabricated using separately optimized low-temperature active layer, contact layer and gate dielectric layer. To achieve good electronic properties for these layers, hydrogen dilution was required.

Transient and Stress Effects in Amorphous Silicon Thin-Film Transistors

1993 ◽  
Vol 297 ◽  
Author(s):  
M. Hack ◽  
R. Weisfield ◽  
M.F. Willums ◽  
G.H. Masterton ◽  
P.G. Lecomber
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Thin Film Transistors ◽  
Elevated Temperatures ◽  
Gate Dielectric ◽  
Drain Current ◽  
Silicon Thin Film ◽  
Slow Decay ◽  
Simulation Results ◽  
Trap Filling

In this paper we present experimental and simulation results of the transient response of amorphous silicon (a-Si) thin film transistors (TFTs) over many orders of magnitude in time after the application of a voltage pulse to the gate. In general three regimes are observed by plotting drain current versus the logarithm of time. At times longer than the carrier transit time and extending up to 1 - 100 msecs, the current rapidly decreases due to trap filling, after which it then slowly decays up until defects are created in the silicon channel when it then finally decays more rapidly again. Our simulation results are in good agreement with the data for the short time trap filling regime, as a function of both gate bias and stress condition. Measurements at elevated temperatures show that the middle slow decay regime is caused by charge injection into interface states or the gate dielectric. Finally we also demonstrate that this slow decay regime does not occur in nin diodes, confirming that it is not caused by defect generation in the a-Si, and is instead related to the presence of the dielectric in a TFT.

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