Novel Growth Techniques for the Fabrication of Photonic Integrated Circuits

1991 ◽  
Vol 240 ◽  
Author(s):  
G. Coudenys ◽  
G. Vermeire ◽  
Y. Zhu ◽  
I. Moerman ◽  
L. Buydens ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Photonic Integrated Circuits ◽  
Vapour Phase ◽  
Vapour Phase Epitaxy ◽  
Integration Schemes ◽  
Recent Developments ◽  
Laser Waveguide ◽  
Special Growth ◽  
And Performance ◽  
Balanced Photodetector

INTRODUCTION:The fabrication of Photonic Integrated Circuits (PIC) requires the development of advanced growth and processing techniques. One of the major problems in the fabrication of PICs is the monolithic integration of passive and active waveguiding structures with a different bandgap. This is schematically shown in figure 1 where a laser, waveguide and detector are integrated on the same substrate. The following relationship between the different bandgaps is required : Eg (detector) < Eg (laser) < Eg (waveguide). One of the most advanced PICs is certainly a coherent receiver chip where a local DFB laser oscillator is integrated with a Y-junction, 3-dB splitter and balanced photodetector pair [1,2,3]. Current integration schemes are mostly based on the use of different epitaxial growth steps to obtain the different bandgap materials on the same substrate. In order to improve yield and performance it is required to reduce the number of growth steps by using special growth techniques. In this paper we will briefly describe some of the recent developments in advanced growth techniques. A more detailed description will be given of our recent work based on selective growth and shadow masked growth using Metal Organic Vapour Phase Epitaxy (MOVPE).

History of HgTe-based photodetectors in Poland

2010 ◽  
Vol 18 (3) ◽  
Author(s):  
A. Rogalski
Keyword(s):  
High Performance ◽  
Flicker Noise ◽  
Vapour Phase ◽  
Fast Response ◽  
Thick Wall ◽  
Vapour Phase Epitaxy ◽  
Stage Of Development ◽  
In Series ◽  
Multiple Cell ◽  
And Performance

AbstractIn Poland, the HgCdTe studies began in 1960 at the Institute of Physics, Warsaw University. The material processing laboratory was created by Giriat and later by Dziuba, Gałązka, and others. Bridgman technique with sealed thick wall quartz ampoules was used to grow material suitable for research and experimental devices. Among the first papers published in 1961 and 1963 there were the Polish works devoted to preparation, doping, and electrical properties of HgCdTe.Infrared detector’s research and development efforts in Poland were concentrated mostly on uncooled market niche. At the beginning, a modified isothermal vapour phase epitaxy has been used for research and commercial fabrication of photoconductive, photoelectromagnetic and other HgCdTe devices. Bulk growth and liquid phase epitaxy were also used. Recently, the fabrication of infrared devices relies on low temperature epitaxial technique, namely metalorganic vapour phase deposition.At present stage of development, the photoconductive and photoelectromagnetic (PEM) detectors are gradually replaced with photovoltaic devices which offer inherent advantages of no electric or magnetic bias, no heat load and no flicker noise. Potentially, photodiodes offer high performance and very fast response. However, conventional photovoltaic uncooled detectors suffer from low quantum efficiency and very low junction resistance. The problems have been solved with advanced band gap engineered architecture, multiple cell heterojunction devices connected in series, and monolithic integration of the detectors with microoptics.In final part of the paper, the Polish achievements in technology and performance of HgMnTe and HgZnTe photodetectors are presented.

Advanced integration schemes for high-functionality/high-performance photonic integrated circuits

2006 ◽  
Author(s):  
James W. Raring ◽  
Matthew N. Sysak ◽  
Anna Tauke-Pedretti ◽  
Matthew Dummer ◽  
Erik J. Skogen ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Photonic Integrated Circuits ◽  
Integration Schemes

The first commercial large-scale InP photonic integrated circuits: current status and performance

2007 ◽  
Author(s):  
Sheila Hurtt ◽  
Andrew G. Dentai ◽  
Jacco L. Pleumeekers ◽  
Atul Mathur ◽  
Ranjani Muthiah ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Photonic Integrated Circuits ◽  
Current Status ◽  
And Performance

Photoelectronic integrated circuits

1989 ◽  
Vol 329 (1603) ◽  
pp. 131-137
Keyword(s):  
Liquid Phase ◽  
Integrated Circuits ◽  
Molecular Beam ◽  
Laser Diodes ◽  
Vapour Phase ◽  
Compound Semiconductor ◽  
Thin Layers ◽  
Semiconductor Materials ◽  
Vapour Phase Epitaxy ◽  
New Process

The encounter of optoelectronics and microelectronics leads to photoelectronic integrated circuits (ICS). The concept is not new, but it has become more feasible in the last couple of years because of advances in the compound semiconductor technologies used to produce laser diodes and photodetectors and GaAs MES ICS. In particular, molecular beam epitaxy and vapour phase epitaxy have shown big improvements so that it is now possible to fabricate well-controlled thin layers of semiconductor, which is difficult using conventional liquid phase epitaxy. In this paper, I discuss the motives for pursuing photoelectronic integration in semiconductor materials and also the relevant essential technologies. I then give examples of monolithic integration at the photonic device level which gives higher performance and higher functionality, and describe prototype photoelectronic integrated circuits highlighting the new process technologies used.

Scanned tip measurement of deep vertical facets on a flat surface: Measuring roughness on gaas laser waveguide mirrors

1993 ◽  
Vol 51 ◽  
pp. 532-533
Author(s):  
Chang Shen ◽  
Phil Fraundorf ◽  
Robert W. Harrick
Keyword(s):  
Integrated Circuits ◽  
Flat Surface ◽  
Scanning Force Microscopy ◽  
Scanning Tunneling ◽  
Tunneling Microscopy ◽  
Force Microscopy ◽  
Optoelectronic Integrated Circuits ◽  
Laser Waveguide ◽  
Scanning Force ◽  
Gaas Laser

Monolithic integration of optoelectronic integrated circuits (OEIC) requires high quantity etched laser facets which prevent the developing of more-highly-integrated OEIC's. The causes of facet roughness are not well understood, and improvement of facet quality is hampered by the difficulty in measuring the surface roughness. There are several approaches to examining facet roughness qualitatively, such as scanning force microscopy (SFM), scanning tunneling microscopy (STM) and scanning electron microscopy (SEM). The challenge here is to allow more straightforward monitoring of deep vertical etched facets, without the need to cleave out test samples. In this presentation, we show air based STM and SFM images of vertical dry-etched laser facets, and discuss the image acquisition and roughness measurement processes. Our technique does not require precision cleaving. We use a traditional tip instead of the T shape tip used elsewhere to preventing “shower curtain” profiling of the sidewall. We tilt the sample about 30 to 50 degrees to avoid the curtain effect.

Characterization of GaAs/AlGaAs quantum wells and quantum wires by chemical lattice imaging

1994 ◽  
Vol 52 ◽  
pp. 736-737
Author(s):  
A. Carlsson ◽  
J.-O. Malm ◽  
A. Gustafsson
Keyword(s):  
Quantum Well ◽  
Quantum Wells ◽  
Quantum Wires ◽  
Vapour Phase ◽  
Quantitative Information ◽  
Lattice Imaging ◽  
Vapour Phase Epitaxy ◽  
Metalorganic Vapour Phase Epitaxy ◽  
High Resolution Images

In this study a quantum well/quantum wire (QW/QWR) structure grown on a grating of V-grooves has been characterized by a technique related to chemical lattice imaging. This technique makes it possible to extract quantitative information from high resolution images.The QW/QWR structure was grown on a GaAs substrate patterned with a grating of V-grooves. The growth rate was approximately three monolayers per second without growth interruption at the interfaces. On this substrate a barrier of nominally Al0.35 Ga0.65 As was deposited to a thickness of approximately 300 nm using metalorganic vapour phase epitaxy . On top of the Al0.35Ga0.65As barrier a 3.5 nm GaAs quantum well was deposited and to conclude the structure an additional approximate 300 nm Al0.35Ga0.65 As was deposited. The GaAs QW deposited in this manner turns out to be significantly thicker at the bottom of the grooves giving a QWR running along the grooves. During the growth of the barriers an approximately 30 nm wide Ga-rich region is formed at the bottom of the grooves giving a Ga-rich stripe extending from the bottom of each groove to the surface.

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