Low-Resistivity Amorphous Silicon for Contacts Using Low-Temperature Rapid Thermal Annealing

1992 ◽  
Vol 258 ◽  
Author(s):  
Lynnita Knoch ◽  
Gordon Tam ◽  
N. David Theodore ◽  
Ron Pennell

ABSTRACTFabrication of SiGe heterojunction bipolar transistors (HBTs) requires a low thermal budget to avoid relaxation of the strained SiGe base layer. Ion implantation is one of the most widely used techniques to achieve contacts. However, due to thermal budget constraints, low temperature rapid thermal annealing (RTA) cycles to activate these implants are insufficient to anneal out all of the implant damage. Polysilicon contacts provide an alternative to ion implantation, but are typically annealed at high temperatures (>950°C) to achieve low sheet resistivity. In this study, amorphous silicon and polycrystalline silicon films were implanted with boron, arsenic, or phosphorus and RTA'd at temperatures from 800°C to 950°C and compared to single crystal silicon with identical implants and RTA cycles. The films were characterized using four-point probe, Hall measurements, TEM (transmission electron microscopy), and SIMS (secondary-ion mass-spectrometry). TEM analysis shows that the amorphous deposition produces larger grains upon RTA due to more rapid grain growth than the polycrystalline deposition. The sheet resistance for the amorphous deposited films is much lower than that of the polycrystalline deposition for all implant conditions. Activations of the implants indicate that the arsenic and phosphorus segregate to the grain boundaries, while the boron does not. The segregation is more significant for the polycrystalline films than for the amorphous films and can be explained by the grain boundary area. For contacts to the SiGe HBT, which requires a low thermal budget, an amorphous deposited silicon film is advantageous over a polycrystalline film at low annealing temperatures because it has lower sheet resistance, less segregation to the grain boundaries, and produces larger grains.

1989 ◽  
Vol 65 (5) ◽  
pp. 2069-2072 ◽  
Author(s):  
R. Kakkad ◽  
J. Smith ◽  
W. S. Lau ◽  
S. J. Fonash ◽  
R. Kerns

1990 ◽  
Vol 182 ◽  
Author(s):  
R. Kakkad ◽  
S. J. Fonash ◽  
P. R. Howell

AbstractPECVD a-Si deposited at 250ºC on 7059 glass was used as precursor material to produce low resistivity large grain doped poly Si. The films doped in the range of 1020−1021 cm-3 with P during growth or by ion implantation wereannealed at 700ºC for times 2 to 5 minutes using RTA. A dopant enhanced grain growth was observed with grain sizes of the order of 3 μm for films of only 2000Å thickness. Resistivity as low as 6x10-4 Ω-cm and mobility as highas 34 cm2 /V-sec. were obtained using this low thermal budget process.These values are comparable to those obtained in the literature using significantly higher annealing temperatures.


2009 ◽  
Vol 12 (9) ◽  
pp. H319 ◽  
Author(s):  
Il-Suk Kang ◽  
Sung-Hun Yu ◽  
Hyun-Sang Seo ◽  
Jeong-Hun Kim ◽  
Jun-Mo Yang ◽  
...  

1998 ◽  
Vol 514 ◽  
Author(s):  
X. W. Lin ◽  
N. Ibrahim ◽  
L. Topete ◽  
D. Pramanik

ABSTRACTA NiSi-based self-aligned silicidation (SALICIDE) process has been integrated into a 0.25 Ion CMOS technology. It involves rapid thermal annealing (RTA) of Ni thin films (300, Å thick) on Si substrates in the temperature range ≈400 - 700 °C. It was found that the NiSi sheet resistance (Rs) gradually decreases with decreasing linewidth. Parameters, such as RTA temperature, substrate dopant (As vs BF2) and structure (single crystal vs poly), were found to have little effects on Rs. NiSi forms a smoother interface with single crystalSi than with poly Si, and has a slightly lower resistivity. MOSFETs based on NiSi show comparable device characteristics to those obtained with Ti SALICIDE. Upon thermal annealing, NiSi remains stable at 450 °C for more than 39 hours. The same is true for 500 °C anneals up to 6 hours, except for NiSi narrow lines (<0.5 μm) on n+ poly Si substrates whose Rs is moderately increased after a 6 hr anneal. This work demonstrates that with an appropriate low-thermal budget backend process, NiSi SALICIDE can be a viable process for deep submicron ULSI technologies.


1996 ◽  
Vol 17 (11) ◽  
pp. 503-505 ◽  
Author(s):  
Hsiao-Yi Lin ◽  
Chun-Yen Chang ◽  
Tan Fu Lei ◽  
Feng-Ming Liu ◽  
Wen-Luh Yang ◽  
...  

2009 ◽  
Vol 156-158 ◽  
pp. 395-400 ◽  
Author(s):  
Ville Vähänissi ◽  
Antti Haarahiltunen ◽  
H. Talvitie ◽  
M.I. Asghar ◽  
Marko Yli-Koski ◽  
...  

Low temperature boron and phosphorous diffusion gettering (BDG and PDG) of iron in Czochralski-grown silicon were experimentally studied. Differences and similarities between the gettering techniques were clarified by using intentionally iron contaminated wafers emphasizing especially the effect of oxygen. Experiments showed that the surprisingly high gettering effects of BDG could be explained by B-Si precipitates. Oxygen precipitation was seen to decrease minority carrier diffusion length after long gettering at low temperatures in both BDG and PDG. In the case of BDG oxygen precipitation affected more as a higher thermal budget was needed to obtain similar sheet resistance to that of PDG. According to experiments the efficiency of BDG can not be concluded from the sheet resistance, whereas the efficiency of PDG can. This has practical influences in a process control environment.


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