Hybrid Amorphous and Polycrystalline Silicon Devices for Large-Area Electronics

1998 ◽  
Vol 508 ◽  
Author(s):  
P. Mei ◽  
J. B. Boyce ◽  
D. K. Fork ◽  
G. Anderson ◽  
J. Ho ◽  
...  

AbstractDistinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and short-channel amorphous silicon thin film transistors have been demonstrated.

1998 ◽  
Vol 507 ◽  
Author(s):  
P. Mei ◽  
J. B. Boyce ◽  
D. K. Fork ◽  
G. Anderson ◽  
J. Ho ◽  
...  

ABSTRACTDistinct features of amorphous and polycrystalline silicon are attractive for large-area electronics. These features can be utilized in a hybrid structure which consists of both amorphous and polycrystalline silicon materials. For example, an extension of active matrix technology is the integration of peripheral drivers for the improvement of reliability, cost reduction and compactness of the packaging for large-area electronics. This goal can be approached by a combination of amorphous silicon pixel switches and polysilicon drivers. A monolithic fabrication process has been developed based on a simple modification of the amorphous silicon transistor process which uses selective area laser crystallization. This approach allows us to share many of the process steps involved in making both the amorphous and polysilicon devices. Another example of the hybrid device structure is a self-aligned amorphous silicon thin film transistor with polysilicon source and drain contacts. The advantages of the self-aligned transistor are reduction of the parasitic capacitance and scaling down of the device dimension. With a selective laser doping technique, self-aligned and shortchannel amorphous silicon thin film transistors have been demonstrated.


2001 ◽  
Author(s):  
YehJiun Tung ◽  
Paul G. Carey ◽  
Patrick M. Smith ◽  
Steven D. Theiss ◽  
Paul Wickboldt ◽  
...  

1989 ◽  
Vol 149 ◽  
Author(s):  
J. G. Shaw ◽  
M. Hack

ABSTRACTWe describe a vertical amorphous silicon thin-film transistor which is easy to fabricate and has a very short channel length that is determined by deposition, not lithography. Our vertical TFTs are compatible with large-area processing techniques andd have suitable terminal characteristics for use in practical circuits. Unlike a conventional thin-film transistor, the current path is primarily parallel to the electric field created by an insulated gate electrode. A two-dimensional computer program is used to analyze these devices and guide their design and optimization. We show how to suppress excessive leakage currents and improve the saturation of the output characteristics by a novel current-blocking technique.


2009 ◽  
Vol 30 (1) ◽  
pp. 36-38 ◽  
Author(s):  
J. H. Oh ◽  
D. H. Kang ◽  
W. H. Park ◽  
J. Jang ◽  
Y. J. Chang ◽  
...  

1984 ◽  
Vol 33 ◽  
Author(s):  
H. C. Tuan

ABSTRACTIn this paper, the amorphous silicon thin film transistor (a-Si:HTFT) technology is reviewed. Its applications to both one- and two-dimensional large-area devices are described. The issues related to the fabrication of TFT arrays on large-area substrates are also discussed.


2000 ◽  
Vol 609 ◽  
Author(s):  
D. Caputo ◽  
L. Colalongo ◽  
F. Irrera ◽  
F. Lemmi ◽  
F. Palma

ABSTRACTPractical use of amorphous silicon stacked-junction color detectors in large-area arrays requires periodic readout of the photo-charge stored in the capacitance of the device by a transient technique of sensing. In any stacked-junction devices, color information is obtained by the “self-biasing” process: during an integration time, the three junctions independently lose charge; during the readout pulse, the capacitances of the three junctions in electrical series are re-charged. Equilibrium is reached after a few cycles, when the charge integrated in a cycle by each junction is the same, and equals the readout charge. The amount of charge is determined by the reverse biased junction and accounts for the light intensity.Dimensioning the amorphous silicon Thin Film Transistor (TFT) used as a pixel switch for the detector is a critical part of the project of a color imager. The actual design determines the self-bias process duration and the readout accuracy. The typical large thickness difference between the detector junctions makes the constraints for the switching process extremely demanding: since a greater capacitance is expected in the thinner top junction detecting blue radiation, the on-resistance must be reduced. Since the front junction does not ensure full rejection of green and red light, a calculation must be performed to extract the information on blue radiation. This requires further precision in the readout process.In this work we present a simulation study of the self-biasing process. Both a-Si:H TFT and the a-Si:H p-i-n-i-p two-color detectors are simulated by a finite-elements two-dimensional simulator ensuring a correct modeling of both the devices. Simulations allow to study in detail the timing and the accuracy of the self-biasing process. Including electrostatic capacitance and trapped charge, a set of design rules for the TFT is achieved in terms of on-state design. Similar considerations can be extended to the case of ATCD three-color detectors.


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