Electrical Characteristics of TaOxNy for High-k MOS Gate Dielectric Applications

2000 ◽  
Vol 611 ◽  
Author(s):  
Kiju Im ◽  
Hyungsuk Jung ◽  
Sanghun Jeon ◽  
Dooyoung Yang ◽  
Hyunsang Hwang
Keyword(s):  
Electron Spectroscopy ◽  
Gate Dielectric ◽  
Tantalum Oxide ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Ammonia Treatment ◽  
High K ◽  
Mos Gate

ABSTRACTIn this paper, we report a process for the preparation of high quality amorphous tantalum oxynitride (TaOxNy) via ammonia annealing of Ta2O5 followed by wet reoxidation for use in gate dielectric applications. Compared with tantalum oxide(Ta2O5), a significant improvement in the dielectric constant was obtained by the ammonia treatment followed by light reoxidation in a wet ambient. We confirmed nitrogen incorporation in the tantalum oxynitride (TaOxNy) by Auger Electron Spectroscopy. By optimizing the nitridation and reoxidation process, we obtained an equivalent oxide thickness of less than 1.6nm and a leakage current of less than 10mA/cm2 at -1.5V. Compared with NH3 nitridation, nitridation of Ta2O5 in ND3 improve charge trapping and charge-to-breakdown characteristics of tantalum oxynitride.

Electrical Characteristics of Crystalline Gd2O3 Film on Si (111): Impacts of Growth Temperature and Post Deposition Annealing

2010 ◽  
Vol 1252 ◽  
Author(s):  
Gang Niu ◽  
Bertrand Vilquin ◽  
Nicolas Baboux ◽  
Guillaume Saint-Girons ◽  
Carole Plossu ◽  
...  
Keyword(s):  
Molecular Beam ◽  
Defect Density ◽  
Oxide Thickness ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Optimal Temperature ◽  
Post Deposition Annealing ◽  
High K ◽  
Electrical Characterizations ◽  
Post Deposition

AbstractThis work reports on the epitaxial growth of crystalline high-k Gd2O3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd2O3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10-2 A/cm2 at |Vg-VFB|=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd2O3 films exhibit good stability and the PDA process can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd2O3/Si (111) capacitor.

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

2011 ◽  
Vol 88 (7) ◽  
pp. 1309-1311 ◽  
Author(s):  
C.H. Fu ◽  
K.S. Chang-Liao ◽  
Y.A. Chang ◽  
Y.Y. Hsu ◽  
T.H. Tzeng ◽  
...  
Keyword(s):  
Leakage Current ◽  
Gate Dielectric ◽  
Oxide Thickness ◽  
Gate Leakage Current ◽  
Equivalent Oxide Thickness ◽  
Gate Leakage ◽  
High K ◽  
High K Gate Dielectric

Experimental Study of Etched Back Thermal Oxide for Optimization of the Si/High-k Interface

2004 ◽  
Vol 811 ◽  
Author(s):  
Joel Barnett ◽  
N. Moumen ◽  
J. Gutt ◽  
M. Gardner ◽  
C. Huffman ◽  
...  
Keyword(s):  
Experimental Study ◽  
Surface Preparation ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Electrical Characteristics ◽  
Equivalent Oxide Thickness ◽  
Gate Stacks ◽  
Thermal Oxide ◽  
High K ◽  
Preparation Techniques

ABSTRACTWe have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Scalability of MOCVD-deposited Hafnium Oxide

2003 ◽  
Vol 765 ◽  
Author(s):  
S. Van Elshocht ◽  
R. Carter ◽  
M. Caymax ◽  
M. Claes ◽  
T. Conard ◽  
...  
Keyword(s):  
Hafnium Oxide ◽  
Interfacial Layer ◽  
Gate Dielectric ◽  
Deposition Process ◽  
Oxide Thickness ◽  
Process Conditions ◽  
Primary Concern ◽  
Gate Electrode ◽  
K Value ◽  
High K

AbstractBecause of aggressive downscaling to increase transistor performance, the physical thickness of the SiO2 gate dielectric is rapidly approaching the limit where it will only consist of a few atomic layers. As a consequence, this will result in very high leakage currents due to direct tunneling. To allow further scaling, materials with a k-value higher than SiO2 (“high-k materials”) are explored, such that the thickness of the dielectric can be increased without degrading performance.Based on our experimental results, we discuss the potential of MOCVD-deposited HfO2 to scale to (sub)-1-nm EOTs (Equivalent Oxide Thickness). A primary concern is the interfacial layer that is formed between the Si and the HfO2, during the MOCVD deposition process, for both H-passivated and SiO2-like starting surfaces. This interfacial layer will, because of its lower k-value, significantly contribute to the EOT and reduce the benefit of the high-k material. In addition, we have experienced serious issues integrating HfO2 with a polySi gate electrode at the top interface depending on the process conditions of polySi deposition and activation anneal used. Furthermore, we have determined, based on a thickness series, the k-value for HfO2 deposited at various temperatures and found that the k-value of the HfO2 depends upon the gate electrode deposited on top (polySi or TiN).Based on our observations, the combination of MOCVD HfO2 with a polySi gate electrode will not be able to scale below the 1-nm EOT marker. The use of a metal gate however, does show promise to scale down to very low EOT values.

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