QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance gm and channel conductance gD using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.