A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP
2005 ◽
Vol 14
(05)
◽
pp. 997-1006
◽
Keyword(s):
A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.
2016 ◽
Vol 4
(2)
◽
pp. 397
2003 ◽
Vol 50
(11)
◽
pp. 892-896
◽
2017 ◽
Vol 31
(19-21)
◽
pp. 1740069
◽
Keyword(s):
2014 ◽
Vol 35
(10)
◽
pp. 105006
◽
2021 ◽
Vol 10
(10)
◽
pp. 101-106
2022 ◽
Vol ahead-of-print
(ahead-of-print)
◽
Keyword(s):
Keyword(s):