As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption.
Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag