A performance Analysis  of DM-DG  and TM-DG TFETs Analytical Models for Low Power Applications

Device Modeling is utilized to engendering incipient device models for the demeanor of the electrical devices predicated on fundamental physics. Modeling of the device may also include the creation of Compact models. An emerging device type of transistor is the Tunnel Field-Effect transistor that achieves compactness and speed during device modeling. This article presents an analytical comparative study of duel material DG TFETs and triple Material DG TFETs with gate oxide structure . Here the implementation of device modeling is done by solving Poisson’s equation with Parabolic Approximation Technique(PAT).The process of formulation of drain current(Id) model is based on integrating the BTBT generation. A Transconductance model of the device is additionally developed utilizing this drain current model of TFET. Surface potential is calculated by utilizing the channel potential model. The electrical properties like Surface potential〖(Ψ〗_(s,i)), Drain current (Id ), and Electric field(Ei) have been compared for both Duel material DG-TFET and Triple material DG-TFET. The comparison statement of DMDG-TFETs and TMDG-TFETs provide improved performance. The analytical model of the device results are compared with simulated results for DMDG TFET and TMDG TFET and good acquiescent is examined.

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A channel-potential-based surface potential model and a turn-on DC channel-potential-based drain current model for fully-depleted poly-Si thin film transistors including tail and deep acceptor-like trap states in bulk

Modern Physics Letters B ◽

10.1142/s0217984920500232 ◽

2019 ◽

Vol 34 (02) ◽

pp. 2050023

Author(s):

Zhen Zhu ◽

Junhao Chu

Keyword(s):

Surface Potential ◽

Potential Model ◽

Coupling Effect ◽

Current Model ◽

Drain Current ◽

Back Surface ◽

Trap States ◽

Deep Acceptor ◽

Fully Depleted ◽

Channel Potential

For fully-depleted polycrystalline silicon thin film transistors including both tail and deep acceptor-like trap states in the bulk and interface charges, a channel-potential-based surface potential model (including front and back surface potential) and a turn-on DC channel-potential-based drain current model are proposed with the effect of the back surface potential considered. Firstly, a channel-potential-based surface potential model is obtained by introducing a channel-potential-based front and back surface potential equation and a channel-potential-based equation describing the coupling effect of the front and back surface potential. Contributions of active acceptors, electrons and trapped charges are all taken into account in this coupling effect. Moreover, by integrating the electron concentration, vertically to the front poly-Si/oxide interface, in the inversion layer, using the average electric field concept and considering the effect of channel potential in the potential of the inversion layer’s ending point, the areal density of the inversion charge is deduced. Furthermore, a channel-potential-based drain current model, avoiding the double numerical integration, is developed with the merit of relative simplification in calculation. By using recursive Simpson rules, this drain current model is calculated by numerical integration with the examining condition. And the above proposed models are verified by 2D-device simulation from MEDICI.

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