scholarly journals A surface-potential-based drain current model suitable for poly-Si thin film transistors with thin body and thin gate oxide

2018 ◽  
Vol 1141 ◽  
pp. 012066
Author(s):  
Zhen Zhu ◽  
Junhao Chu
Keyword(s):  
Thin Film ◽  
Surface Potential ◽  
Thin Film Transistors ◽  
Current Model ◽  
Drain Current ◽  
Gate Oxide ◽  
Thin Body ◽  
Thin Gate Oxide ◽  
Si Thin Film

Analytical surface-potential-based drain current model for amorphous InGaZnO thin film transistors

2013 ◽  
Vol 114 (18) ◽  
pp. 184502 ◽  
Author(s):  
A. Tsormpatzoglou ◽  
N. A. Hastas ◽  
N. Choi ◽  
F. Mahmoudabadi ◽  
M. K. Hatalis ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface Potential ◽  
Thin Film Transistors ◽  
Current Model ◽  
Drain Current ◽  
Amorphous Ingazno

Surface-Potential-Based Drain Current Model for Polycrystalline Silicon Thin-Film Transistors

2008 ◽  
Vol 47 (10) ◽  
pp. 7798-7802 ◽  
Author(s):  
Hiroshi Tsuji ◽  
Tsuyoshi Kuzuoka ◽  
Yuji Kishida ◽  
Yoshiyuki Shimizu ◽  
Masaharu Kirihara ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface Potential ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
Current Model ◽  
Drain Current ◽  
Silicon Thin Film

scholarly journals Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1016
Author(s):  
Silvestre Salas-Rodríguez ◽  
Francisco López-Huerta ◽  
Agustín L. Herrera-May ◽  
Joel Molina-Reyes ◽  
Jaime Martínez-Castillo
Keyword(s):  
Thin Film ◽  
Numerical Simulations ◽  
Density Of States ◽  
Thin Film Transistors ◽  
High Performance ◽  
Current Model ◽  
Drain Current ◽  
Absolute Error ◽  
Threshold Region ◽  
Large Area

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.

SURFACE POTENTIAL DISTRIBUTION MODEL BASED ON ANALYTICAL CHANNEL POTENTIAL APPROXIMATION FOR ULTRA-THIN BODY POLY-SI THIN FILM TRANSISTORS IN LINEAR REGION

2017 ◽  
Vol 24 (08) ◽  
pp. 1750108 ◽  
Author(s):  
ZHEN ZHU ◽  
JUNHAO CHU
Keyword(s):  
Thin Film ◽  
Surface Potential ◽  
Thin Film Transistors ◽  
Potential Distribution ◽  
Distribution Model ◽  
Thin Body ◽  
Distribution Models ◽  
Linear Region ◽  
Interface Charge ◽  
Channel Potential

For ultra-thin body polycrystalline silicon thin film transistors, the surface potential distribution model, in the linear region, based on the analytical channel potential (CP) approximation is presented without or with the interface charge, respectively. For the purpose of simplifying the process of the solution and with the merit of the clear physical picture, both the surface potential distribution models in the linear region are developed, attributed to the deduction of the analytical CP approximation, by solving one-dimensional Poisson’s equation and applying the Gauss’s law at the poly-Si/oxide interface. Furthermore, the quantitative conditions for the model validity are also developed for both surface potential distribution models. Under these proposed quantitative conditions, both models are verified by the two-dimensional-device simulation on the normalized channel distance under various gate voltages, drain voltages, channel lengths and various areal interface charge densities for the consideration of the interface charge.

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