RESEARCH OF PECULIARITIES OF ERROR DETECTION ON THE OUTPUTS OF PROGRAMMABLE LOGIC INTEGRATED CIRCUITS WITH FUNCTIONAL CONTROL BASED ON MODULAR CODES WITH SUMMATION

2021 ◽  
Vol 7 (3) ◽  
pp. 477-495
Author(s):  
A. V. Pashukov ◽  

The article provides examples of the use of programmable logic integrated circuits in various industries. Possible faults in FPGA blocks and their difference from faults in programmable logic arrays are described. Particular attention is paid to the failures of the LUT element. Features of the organization of technical diagnostics systems operating in the operating mode of the objects of diagnostics for combinational logic devices, implemented on the basis of programmable logic integrated circuits are described. Using the example of modular summation codes, it is shown that the known approaches to organizing such systems for devices implemented on a valve basis can be directly applied to devices of the type under consideration. Since malfunctions in the form of errors are recorded, and not the malfunctions themselves, the approaches to the organization of diagnostic systems are universal. It also provides a comparative characteristic of modular sum codes depending on the code module. A code has been proposed that will detect all faults in the example under study.

Author(s):  
Apangshu Das ◽  
Sambhu Nath Pradhan

Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.


2021 ◽  
pp. 50-57
Author(s):  
V. I. Matveev

The article summarizes the results of the MetrolExpo exhibition, which was held for the first time online. The event focused on instrumentation-demonstration and discussion of the possibilities of modern measuring equipment, analysis of new methods and technologies of accurate measurements that have appeared in recent years. The latest developments, devices and systems for conducting measurements, tests, technical diagnostics, analytical studies, production and functional control from the largest Russian and foreign manufacturers were demonstrated.


2009 ◽  
Vol 1 (1) ◽  
Author(s):  
В. М. Опанасенко ◽  
О. М. Лісовий ◽  
Є. В. Сорока

1982 ◽  
Author(s):  
Joseph C. Logue ◽  
Walter J. Kleinfelder ◽  
J. Randal Moulic ◽  
Paul Lowry ◽  
Wei-Wha Wu

1993 ◽  
Vol 30 (3) ◽  
pp. 216-223 ◽  
Author(s):  
Ilya Levin

Matrix model of logical simulator within spreadsheet This paper examines the use of spreadsheets for simulation of logical control units. A matrix model is proposed for this aim. The use of this model is appropriate both for teaching and learning of simulation of a specific type of integrated circuit — Programmable Logic Arrays — and also for any type of control unit representable in the form of a logical function system.


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