scholarly journals Prognosis of Manufacturing of a Two-Level Current-Mode Logic Gate in Latch Based on Heterostructures to Increase Density of their Elements with Account Miss-Match Induced Stress and Porosity of Materials on Technological Process. On Approach for Optimization of Manufacturing

1990 ◽  
Vol 01 (01) ◽  
pp. 101-124 ◽  
Author(s):  
P.K. TIEN

The needs for multi-gigabits/second digital electronics in advanced lightwave systems have motivated R & D for the next generation of high speed bipolar technology. The speed of the digital circuit may be estimated from the propagation delay of the logic gate. We discuss physics of the delay and show that it is fundamentally limited by the time needed for turning on (off) a transistor and by the time for charging (discharging) of capacitances in the circuit. We present a large-signal theory based on a charge-control model for the calculation of these limits. The results obtained for emitter coupled logic and current mode logic are used to analyze current technologies of silicon bipolar and GaAs HBTs.


10.11591/550 ◽  
2016 ◽  
Vol 5 (1) ◽  
Author(s):  
J Princy Joice ◽  
M Anitha ◽  
I Rexlin Sheeba

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