scholarly journals ON APPROACH TO OPTIMIZE MANUFACTURING OF A TWO-LEVEL CURRENT-MODE LOGIC GATES IN A MULTIPLEXER BASED ON FIELD-EFFECT HETEROTRANSISTORS TO INCREASE DENSITY OF THEIR ELEMENTS. INFLUENCE OF MISMATCH INDUCED STRESS AND POROSITY OF MATERIALS ON TECHNOLOGICAL PROCESS

2020 ◽  
Vol 21 (1) ◽  
pp. 27-77
Author(s):  
E. L. Pankratov ◽  
Keyword(s):  
Technological Process ◽  
Field Effect ◽  
Logic Gates ◽  
Current Mode ◽  
Current Mode Logic ◽  
Induced Stress

Increasing the Density of Field-Effect Heterotransistors in an Amplifier Flipped Voltage Follower Mirrors with Account of Miss-Match Induced Stress

2021 ◽  
Vol 8 (1) ◽  
Keyword(s):  
Integrated Circuits ◽  
Field Effect ◽  
Analytical Approach ◽  
Field Effect Transistors ◽  
Current Mode ◽  
Instrumentation Amplifier ◽  
Flipped Voltage Follower ◽  
Induced Stress ◽  
Voltage Follower ◽  
Specific Configuration

In this paper, we introduce an approach to increase density of field-effect transistors framework current mode instrumentation amplifier flipped voltage follower mirrors. The approach we consider for manufacturing of the inverter in heterostructure with specific configuration. Several required areas of the heterostructure should be doped by diffusion or ion implantation. After that dopant and radiation defects should by annealed framework optimized scheme. We also consider an approach to decrease the value of mismatch-induced stress in the considered heterostructure. We also introduce an analytical approach to analyze mass and heat transport in heterostructures during manufacturing of integrated circuits with account mismatch-induced stress.

scholarly journals MOS Current Mode Logic with Capacitive Coupling

2012 ◽  
Vol 2012 ◽  
pp. 1-7 ◽  
Author(s):  
Kirti Gupta ◽  
Neeta Pandey ◽  
Maneesha Gupta
Keyword(s):  
Analytical Model ◽  
Digital Circuits ◽  
Logic Gates ◽  
Current Mode ◽  
Cmos Technology ◽  
Capacitive Coupling ◽  
Ring Oscillator ◽  
Switching Speed ◽  
Current Mode Logic

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18 μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application.

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