A Monolithic Stochastic Computing Architecture for Energy and Area Efficient Arithmetic

As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence, deep learning, and Big-data [1-4], a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates [5, 6]. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) [7, 8] technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, makes it less attractive. Memristor [9-11] and spin-based devices [12-15] offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here we overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors. Our monolithic and non-von Neumann SC architecture consumes a miniscule amount of energy < 1 nano Joules for s-bit generation and to perform arithmetic operations and occupy small hardware footprint highlighting the benefits of SC.