scholarly journals Design and analysis of SHE-assisted STT MTJ/CMOS logic gates

2021 ◽  
Author(s):  
Prashanth Barla ◽  
Vinod Kumar Joshi ◽  
Somashekara Bhat
Keyword(s):  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Orbit Interaction ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Oxide Semiconductor ◽  
Metal Materials ◽  
Power Delay Product

AbstractWe have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

Performance analysis of differential spin hall effect (DSHE)-MRAM-based logic gates

Circuit World ◽  
2019 ◽  
Vol 45 (4) ◽  
pp. 300-310
Author(s):  
Piyush Tankwal ◽  
Vikas Nehra ◽  
Sanjay Prajapati ◽  
Brajesh Kumar Kaushik
Keyword(s):  
Hall Effect ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Cmos Technology ◽  
Spin Transfer Torque ◽  
Spin Hall Effect ◽  
Oxide Semiconductor ◽  
Content Type

Purpose The purpose of this paper is to analyze and compare the characteristics of hybrid conventional complementary metal oxide semiconductor/magnetic tunnel junction (CMOS/MTJ) logic gates based on spin transfer torque (STT) and differential spin Hall effect (DSHE) magnetic random access memory (MRAM). Design/methodology/approach Spintronics technology can be used as an alternative to CMOS technology as it is having comparatively low power dissipation, non-volatility, high density and high endurance. MTJ is the basic spin based device that stores data in form of electron spin instead of charge. Two mechanisms, namely, STT and SHE, are used to switch the magnetization of MTJ. Findings It is observed that the power consumption in DSHE based logic gates is 95.6% less than the STT based gates. DSHE-based write circuit consumes only 5.28 fJ energy per bit. Originality/value This paper describes how the DSHE-MRAM is more effective for implementing logic circuits in comparison to STT-MRAM.

scholarly journals Modelling amorphous computations with transcription networks

2009 ◽  
Vol 6 (suppl_4) ◽  
Author(s):  
Zack Booth Simpson ◽  
Timothy L. Tsai ◽  
Nam Nguyen ◽  
Xi Chen ◽  
Andrew D. Ellington
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Nand Gate ◽  
Electronic Information ◽  
Logical Operations ◽  
Underlying Basis ◽  
Transcription Networks

The power of electronic computation is due in part to the development of modular gate structures that can be coupled to carry out sophisticated logical operations and whose performance can be readily modelled. However, the equivalences between electronic and biochemical operations are far from obvious. In order to help cross between these disciplines, we develop an analogy between complementary metal oxide semiconductor and transcriptional logic gates. We surmise that these transcriptional logic gates might prove to be useful in amorphous computations and model the abilities of immobilized gates to form patterns. Finally, to begin to implement these computations, we design unique hairpin transcriptional gates and then characterize these gates in a binary latch similar to that already demonstrated by Kim et al . (Kim, White & Winfree 2006 Mol. Syst. Biol. 2 , 68 (doi:10.1038/msb4100099)). The hairpin transcriptional gates are uniquely suited to the design of a complementary NAND gate that can serve as an underlying basis of molecular computing that can output matter rather than electronic information.

scholarly journals A Novel Domino Logic with Modified Keeper in 16nm CMOS Technology

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Anu Mehra ◽  
Smita Singhal ◽  
Upendra Tripathi
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Sleep Mode ◽  
Domino Logic ◽  
Power Delay Product ◽  
Or Gate

Domino logic is a clocked CMOS (Complementary Metal-Oxide Semiconductor) logic with fewer transistors than static CMOS logic. A PMOS (P-type Metal-Oxide Semiconductor) transistor, known as “keeper”, is included in the design to improve the noise tolerance performance and to reduce the leakage current. The aspect ratio i.e. W/L of the keeper (W=width and L=length) is kept low for the correct functionality of the domino logic. This paper proposes a domino logic with modified keeper in order to improve the circuit with respect to power and area as compared to various existing techniques of domino logic i.e. clock delayed domino logic (CDD), high speed domino logic (HSD), multi threshold high speed domino logic (MHSD), clock delayed sleep mode domino logic (CDSMD), sleep switch domino logic (SSDD), PMOS only sleep switch domino logic (PSSDD), reduced delay variations domino logic (RDVD) and Foot Driven Stack Transistor Domino Logic (FDSTDL). The proposed as well as existing domino logics, for 8-input as well as 16-input OR gate in 16nm CMOS technology, are simulated for different values of W/L of keeper with W/L ratio ranging from 1 to 6. The power-delay-product(PDP) of proposed design has improved as compared to the existing designs. For 8-input OR gate and W/L=6, PDP had improved to maximum of 99.99% for CDD and minimum of 38.09% for SSDD.

scholarly journals A Monolithic Stochastic Computing Architecture for Energy and Area Efficient Arithmetic

2022 ◽  
Author(s):  
Harikrishnan Ravichandran ◽  
Yikai Zheng ◽  
Thomas Schranghamer ◽  
Nicholas Trainor ◽  
Joan Redwing ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Logic Gates ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Attractive Alternative ◽  
Two Dimensional ◽  
Arithmetic Operations ◽  
Von Neumann ◽  
Stochastic Computing ◽  
Simple Logic

Abstract As the energy and hardware investments necessary for conventional high-precision digital computing continues to explode in the emerging era of artificial intelligence, deep learning, and Big-data [1-4], a change in paradigm that can trade precision for energy and resource efficiency is being sought for many computing applications. Stochastic computing (SC) is an attractive alternative since unlike digital computers, which require many logic gates and a high transistor volume to perform basic arithmetic operations such as addition, subtraction, multiplication, sorting etc., SC can implement the same using simple logic gates [5, 6]. While it is possible to accelerate SC using traditional silicon complementary metal oxide semiconductor (CMOS) [7, 8] technology, the need for extensive hardware investment to generate stochastic bits (s-bit), the fundamental computing primitive for SC, makes it less attractive. Memristor [9-11] and spin-based devices [12-15] offer natural randomness but depend on hybrid designs involving CMOS peripherals for accelerating SC, which increases area and energy burden. Here we overcome the limitations of existing and emerging technologies and experimentally demonstrate a standalone SC architecture embedded in memory based on two-dimensional (2D) memtransistors. Our monolithic and non-von Neumann SC architecture consumes a miniscule amount of energy < 1 nano Joules for s-bit generation and to perform arithmetic operations and occupy small hardware footprint highlighting the benefits of SC.

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