scholarly journals High-Performance and Energy-Efficient Fault Tolerance FPGA-to-FPGA Communication

2021 ◽  
Author(s):  
Naresh Kumar Reddy ◽  
Swamy Cherukuru ◽  
Veena Vani ◽  
Vishal Reddy
Keyword(s):  
Error Detection ◽  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Key Factors ◽  
Error Detection And Correction ◽  
Performance Error ◽  
Increasing Demand ◽  
Accuracy Performance ◽  
Or Applications

Abstract These days, due to the increasing demand for high speed and parallel computation, several real world applications and systems include multiple FPGAs in them. Due to this, FPGAs often need to communicate among them. So, communication between the FPGAs is one of the key factors that determines the accuracy, performance and correctness of the entire multiple FPGAs systems or applications. This paper presents the design of an efficient multi-bit fault tolerant communication system for FPGA-to-FPGA communication. The proposed design is synthesized and also simulated through Vivado design suit 2018.3 and was communicated with two Kintex-7 FPGA boards. When compared with the existing FPGA-to-FPGA communication and inter FPGA communication designs, the proposed design have higher performance, error detection and correction capability.

Optimized Parity-Based Error Detection and Correction Methods for Residue Number System

2018 ◽  
Vol 28 (01) ◽  
pp. 1950002 ◽  
Author(s):  
Adib Armand ◽  
Somayeh Timarchi ◽  
Hossein Mahdavi
Keyword(s):  
Fault Tolerance ◽  
Error Detection ◽  
High Speed ◽  
Fault Tolerant ◽  
Number System ◽  
Low Complexity ◽  
Residue Number System ◽  
Cell Library ◽  
Error Detection And Correction ◽  
Residue Number

Residue Number System (RNS) has been extensively used in high-speed applications. It inherits the advantages of parallelism and modularity, which lead to fault tolerance property. Since carry propagation is limited to each module in RNS, errors do not propagate inter-moduli. Indeed, due to the restriction in carry propagation and fault tolerance property, RNS can be promisingly fast and reliable that makes it a favorable encoding for the digital systems which are highly prone to noise like communication channels. By adding some extra moduli, the so-called redundant RNS (RRNS) is gained. Although several methods around RRNS have already been proposed in the literature, the structures without need for extra moduli have not been introduced yet. This paper addresses three Error Detection and Correction (EDC) schemes for RNS based on parity structures. Using these techniques, the low power fault-tolerant RNS methods with low complexity are presented. Synthesis results using 180[Formula: see text]nm CMOS standard cell library show that the proposed architectures for the three-moduli set [Formula: see text] are in average 17%, 52% and 44% more efficient than the conventional RRNS in terms of delay, power consumption, and area overhead, respectively, without losing the EDC capability.

Experimental assessment of the dynamic stiffness of a fault-tolerant fly-by-wire hydraulic actuator

2012 ◽  
Vol 226 (6) ◽  
pp. 679-690 ◽  
Author(s):  
G Di Rito ◽  
R Galatolo
Keyword(s):  
High Speed ◽  
High Performance ◽  
Position Control ◽  
Fault Tolerant ◽  
Dynamic Stiffness ◽  
Feasibility Studies ◽  
Hydraulic Actuator ◽  
Dynamic Interactions ◽  
Flight Controls ◽  
Vibration Tests

The stiffness of an actuator depends on the closed-loop position control (architecture and parameters), on the load frequency, and, for fault-tolerant actuators, on the operative mode. The stiffness response is of basic importance for the design of actuators for primary flight controls, especially for high-performance aircrafts. Actually, during flight conditions characterized by high speed and high angle-of-attack, the dynamic interactions between aircraft structure, actuator, and aerodynamic loads can induce aeroservoelastic effects, which, if not controlled, can imply performance degradation and even instability. The study and the compensation of such concerns require the assessment of the resonant frequencies of the aeroservoelastic system, which can be performed only by characterizing the dynamic stiffness of the actuator. This article reports the experimental activities carried out for the characterization of the stiffness response of a fault-tolerant fly-by-wire actuator for the primary flight controls of a modern jet trainer, starting from the feasibility studies of the experiments up to the execution of the vibration tests. The actuator stiffness performance is evaluated in different fail-operative modes by artificially injecting hydraulic and electrical failures, and the experimental data are interpreted by means of an LTI model of the flight actuator, highlighting and discussing the effects that the failures induce on the stiffness performance.

Design of High-Speed Decoder for New High-Speed Bus

2010 ◽  
Vol 20-23 ◽  
pp. 958-962
Author(s):  
Wei Gong Zhang ◽  
Bo Yang ◽  
Rui Ding ◽  
Yong Qin Hu
Keyword(s):  
Error Correction ◽  
Intelligent Control ◽  
Error Detection ◽  
High Speed ◽  
Critical Path ◽  
Speed Error ◽  
Error Detection And Correction ◽  
Traditional Algorithm ◽  
New Type ◽  
Correction System

This paper presents a new type of high-speed error correction for the requirements of new high-Speed Bus. Use RS (255, 239). Not only optimization traditional algorithm, but also design bidirectional synchronous calculated adjoint form module, Fast B-M algorithm module. and full parallel Chien Search module. These design used in new high-Speed Bus, Larger than usual decoder designed to significantly shorten the critical path decoding, and achieve continuous decoding. In addition, this error correction system separated error detection and correction module modules, And after error detection module add intelligent control, which reduced the complexity and power consumption of equipment. The error correction system design for the requirements of the new bus which speed is above 400m / s.

scholarly journals SEC-TAED based Error Detection and Correction Technique for Data Transmission Systems

2018 ◽  
Vol 10 (2) ◽  
pp. 696
Author(s):  
Mr. G. Manikandan ◽  
Dr. M. Anand
Keyword(s):  
Error Detection ◽  
Gaussian Noise ◽  
Data Transmission ◽  
High Speed ◽  
Additive White Gaussian Noise ◽  
Hamming Code ◽  
Correction Technique ◽  
Error Detection And Correction ◽  
Placement Algorithm ◽  
Original Information

<p>In the OFDM communication system channel encoder and decoder is the part of the architecture. OFDM channel is mostly affected by Additive White Gaussian Noise (AWGN) in which bit flipping of original information leads to fault transmission in the channel. To overcome this problem by using hamming code for error detection and correction. Hamming codes are more attractive and it easy to process the encoding and decoding with low latency. In general the hamming is perfectly detected and corrects the single bit error. In this paper, design of single Error Correction-Triple Adjacent Error Detection (SEC-TAED) codes with bit placement algorithm is presented with less number of parity bits. In the conventional Double Adjacent Error Detection (DAED) and Hamming (13, 8) SEC-TAED are process the codes and detects the error, but it require more parity bits for performing the operation. The higher number of parity bits causes processing delay. To avoid this problem by proposed the Hamming (12, 8) SEC-TAED code, it require only four parity bits to perform the detection process. Bit-reordered format used in the method increases the probability detection of triple adjacent error. It is more suitable for efficient and high speed communication.</p>

scholarly journals Algorithm for Clustering the Moduli of RNS for the Application of Optimization of Time Complexity in Standard Cipher System

2020 ◽  
Vol 9 (7) ◽  
pp. 92-97
Keyword(s):  
High Speed ◽  
High Performance ◽  
Fault Tolerant ◽  
Number System ◽  
Residue Number System ◽  
New Method ◽  
Residue Number ◽  
Residue Numbers ◽  
Performance Computing ◽  
Selection Of

Residue number system (RNS) has emerged as a knocking field of research due to its high speed, fault tolerant, carry free and parallel characteristics. Due to these features it has got important role in high performance computing especially with reduced delay. There are various algorithms have been found as a result of the research with respect to RNS. Additionally, since RNS reduces word length due to the modular operations, its computations are faster compared to binary computations. But the major challenges are the selection of moduli sets for the forward (decimal to residue numbers) and reverse (residue numbers to decimal) conversion. RNS performance is purely depending on how efficiently an algorithm computes / chooses the moduli sets [1]-[6]. This paper proposes new method for selecting the moduli sets and its usage in cryptographic applications based on Schonhage modular factorization. The paper proposes six moduli sets {6qk1, 6qk+1, 6qk+3, 6qk+5, 6qk+7, 6qk+11} for the RNS conversions but the Schonhage moduli sets are expressed as the exponents that creates a large gap between the moduli’s computed. Hence, a new method is proposed to for computing moduli sets that helps in representing all the decomposed values approximately in the same range.

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