High-Performance Photonic Analog-to-Digital Converter and Low-Noise Mode-Locked Fiber Lasers

2003 ◽  
Author(s):  
Marc Currie
Keyword(s):  
Fiber Lasers ◽  
High Performance ◽  
Low Noise ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital

scholarly journals A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System

Micromachines ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 114
Author(s):  
Dongdong Chen ◽  
Xinhui Cui ◽  
Qidong Zhang ◽  
Di Li ◽  
Wenyang Cheng ◽  
...  
Keyword(s):  
High Resolution ◽  
Integrated Circuits ◽  
High Performance ◽  
Imaging System ◽  
Ultrasonic Imaging ◽  
Pipelined Adc ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Analog To Digital ◽  
Different Types

As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. The performance of integrated circuits (ICs) in portable UIS obviously affects the effectiveness and quality of ultrasonic imaging. In the ICs for UIS, the analog-to-digital converter (ADC) is used to complete the conversion of the analog echo signal received by the analog front end into digital for further processing by a digital signal processing (DSP) or microcontroller unit (MCU). The accuracy and speed of the ADC determine the precision and efficiency of UIS. Therefore, it is necessary to systematically review and summarize the characteristics of different types of ADCs for UIS, which can provide valuable guidance to design and fabricate high-performance ADC for miniaturized high resolution UIS. In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced. In addition, comparisons and discussions of different types of ADCs are presented. Finally, this paper is summarized, and presents the challenges and prospects of ADC ICs for miniaturized high resolution UIS.

A Low Power, Precision SAR Analog to Digital Converter for High Temperature Applications

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000053-000057
Author(s):  
Jeff Watson ◽  
Maithil Pachchigar
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
High Reliability ◽  
Data Converters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Data Converter ◽  
Precision Data ◽  
Analog To Digital

A growing number of industries are calling for low power electronics that operate reliably at temperatures of 175°C and higher. Many of these applications require a precision data acquisition signal chain in order to digitize analog data so that it can be collected and processed. Designing circuits that meet these needs can be very challenging, requiring a data converter that can deliver high performance and reliability in these harsh environments. There are currently a very limited number of integrated circuits commercially available that are specified for operation at these temperatures, and no low power precision data converters with sample rates greater than 100kSPS. This paper presents a new 210°C rated precision analog to digital converter capable of sample rates up to 600 kSPS with 16 bit resolution while maintaining low power consumption and packaged in a small form factor. We will explore the converter architecture of this ADC, present initial test results, and show how high reliability is achieved through qualification and advanced packaging techniques.

scholarly journals Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 137 ◽  
Author(s):  
Bo Gao ◽  
Xin Li ◽  
Jie Sun ◽  
Jianhui Wu
Keyword(s):  
High Resolution ◽  
Low Noise ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Signal To Noise ◽  
Analog To Digital ◽  
High Bandwidth

The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW.

scholarly journals A 12-bit 30 MS/s Successive Approximation-Register Analog-to-Digital Converter with Foreground Digital Calibration Algorithm

Symmetry ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 165
Author(s):  
Shouping Li ◽  
Yang Guo ◽  
Jianjun Chen ◽  
Bin Liang
Keyword(s):  
Successive Approximation ◽  
High Speed ◽  
Low Noise ◽  
Digital Calibration ◽  
Cmos Process ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Dynamic Comparator ◽  
Analog To Digital ◽  
Calibration Algorithm

This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high speed, high precision, and low noise. The foreground digital calibration algorithm provides high speed with minimal area consumption. This design is implemented on a 12-bit 30 MS/s SARADC with a standard 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) process. The simulation Nyquist 68.56 dB signal-to-noise-and-distortion ratio (SNDR) and 84.45 dBc spurious free dynamic range (SFDR) at 30 MS/s, differential nonlinearity (DNL) and integral nonlinearity (INL) are within 0.64 Least Significant Bits (LSB) and 1.3 LSB, respectively. The ADC achieves an effective number of bits (ENOB) of 11.08 and a figure-of-merit (FoM) of 39.45 fJ/conv.-step.

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