Software Tool Aiding Analysis and Design of Low-Power Parallel Prefix Adders

2021 ◽  
Author(s):  
Ireneusz Brzozowski
Keyword(s):  
Low Power ◽  
Software Tool ◽  
Analysis And Design ◽  
Parallel Prefix ◽  
Prefix Adders

scholarly journals Low Power High Speed Arithmetic Circuits

2019 ◽  
Vol 8 (2) ◽  
pp. 807-813 ◽  
Keyword(s):  
Low Power ◽  
System Design ◽  
High Speed ◽  
Arithmetic Circuits ◽  
Booth Multiplier ◽  
Vedic Multiplier ◽  
Vlsi System ◽  
Parallel Prefix ◽  
Prefix Adders ◽  
Vlsi System Design

In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

Low Power Parallel Prefix Adder

2014 ◽  
Vol 573 ◽  
pp. 194-200 ◽  
Author(s):  
P. Kowsalya ◽  
M. Malathi ◽  
Palaniappan Ramanathan
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Fundamental Operation ◽  
Parallel Prefix ◽  
Power Delay Product ◽  
Prefix Adder ◽  
Prefix Adders

Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

A Low-Power Variable-Gain Amplifier With Improved Linearity: Analysis and Design

2012 ◽  
Vol 59 (10) ◽  
pp. 2176-2185 ◽  
Author(s):  
Zhiming Chen ◽  
Yuanjin Zheng ◽  
Foo Chung Choong ◽  
Minkyu Je
Keyword(s):  
Low Power ◽  
Variable Gain Amplifier ◽  
Analysis And Design ◽  
Variable Gain
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