Low Power High Speed Arithmetic Circuits
2019 ◽
Vol 8
(2)
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pp. 807-813
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Keyword(s):
In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.
2020 ◽
Vol 18
(03)
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pp. 2050002
Keyword(s):
2021 ◽
Vol 12
(3)
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pp. 5673-5683
Keyword(s):
Keyword(s):
2021 ◽
Vol 1979
(1)
◽
pp. 012066
Keyword(s):
2020 ◽
Vol 9
(4)
◽
pp. 615-623
2018 ◽
Vol 7
(2.7)
◽
pp. 733
Keyword(s):