Low Power Parallel Prefix Adder

2014 ◽  
Vol 573 ◽  
pp. 194-200 ◽  
Author(s):  
P. Kowsalya ◽  
M. Malathi ◽  
Palaniappan Ramanathan
Keyword(s):  
Low Power ◽  
Power Saving ◽  
Fundamental Operation ◽  
Parallel Prefix ◽  
Power Delay Product ◽  
Prefix Adder ◽  
Prefix Adders

Addition is a fundamental operation of all Arithmetic and Logic Units (ALU).The speed of addition operation decides the computational frequency of ALU. In order to improve the performance of the binary adder, the parallel prefix adder are preferred. There are various parallel prefix adders available. This work focuses on designing 8-bit prefix adders such as Brent Kung ,Kogge Stone and Sklansky adders using GDI technique. The performance of these GDI based prefix adders are compared with that of CMOS based prefix adder. GDI based prefix adders out performs CMOS based prefix adders in terms of power delay product (PDP). The design is implemented and simulated by DSCH2 and MICROWIND tool .The simulation result reveal about 31%,40% and 50 % of power saving is attained and the number of transistors also reduced.

Performance Analysis of Various Multipliers Using 8T-full Adder with 180nm Technology

2020 ◽  
Vol 13 (6) ◽  
pp. 864-870
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Fundamental Operation ◽  
Wallace Tree ◽  
Power Delay Product ◽  
The Comparative Study ◽  
Wallace Tree Multiplier

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.

Design of high-speed low-power parallel-prefix adder trees in nanometer technologies

2013 ◽  
Vol 42 (7) ◽  
pp. 731-743 ◽  
Author(s):  
Stefania Perri ◽  
Marco Lanuzza ◽  
Pasquale Corsonello
Keyword(s):  
Low Power ◽  
High Speed ◽  
Parallel Prefix ◽  
Prefix Adder

scholarly journals Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders

2018 ◽  
Vol 7 (2) ◽  
pp. 115
Author(s):  
Nehru.K K ◽  
Nagarjuna T ◽  
Somanaidu U
Keyword(s):  
High Performance ◽  
Digital Signal ◽  
Digital Signal Processors ◽  
Transmission Technique ◽  
Look Ahead ◽  
Parallel Prefix ◽  
Prefix Adder ◽  
Signal Processors ◽  
Prefix Adders ◽  
Better Than

<span>Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes<strong> </strong>with the lowest transistor<strong> </strong>count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.</span>

scholarly journals Full Adder for Low Power Applications

2020 ◽  
Vol 9 (4) ◽  
pp. 2682-2687
Keyword(s):  
Low Power ◽  
Processing System ◽  
Full Adder ◽  
Cmos Technology ◽  
Fundamental Operation ◽  
Dynamic Power ◽  
Power Delay Product ◽  
Electronic Processing

In an electronic processing system, addition of binary numbers is a fundamental operation. A one bit low power hybrid FA(full adder) is shown in showing performance improvisation by analysis and comparing with other conventional adders. 1 bit low power hybrid full adder is considered as a good way for enhancing the speed of the circuit in comparison with other conventional circuits of full adders. In that analysis paper, one bit low power hybrid FA(full adder) is implemented by EDA tool and the simulation is analysis by using generic 90nm CMOS technology at 5 volts and comparison is done at various voltages with other conventional full adders. For comparing 1 bit low power hybrid full adder with other conventional adders at various parameters such as static and dynamic power usage, delay & pdp (power delay product) are taken into consideration to show that 1 bit low power hybrid full adder is most suitable for various low power applications.

scholarly journals Design a High Speed Multiplier using Two Phase PPA

2019 ◽  
Vol 8 (11S2) ◽  
pp. 146-149
Keyword(s):  
High Speed ◽  
Two Phase ◽  
Ripple Carry Adder ◽  
Product Generation ◽  
Different Types ◽  
Effective System ◽  
Parallel Prefix ◽  
Three Stages ◽  
Prefix Adder ◽  
Prefix Adders

Basically, multiplier is an efficient superconductor logic which performs various switching operation. Here different types of adders are analysed using different methodologies. In this paper we introduced a multiplier using proposed PPA. It uses parallel prefix adders in their reduction phase and it is an effective system for faster results and optimised. The entire operation of proposed system depends upon three stages they are multiplier partial product generation, reduction stages and parallel prefix adder which is discussed in below sections. The delay gets reduced by achieving low logical depth in the system. So the Proposed system reduces the delay. From the proposed system we can observe that there is a reduction in delay and complexity. Compared to ripple carry adder and carry save adder, proposed system gives better results.

scholarly journals Design and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based

2019 ◽  
Vol 8 (6S3) ◽  
pp. 2181-2182 ◽  
Keyword(s):  
Metal Oxide ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Input Information ◽  
Design And Implementation ◽  
Parallel Prefix ◽  
Distinctive Structure ◽  
Prefix Adder ◽  
Prefix Adders

Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information

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