scholarly journals Parametric Decimal Division using Hardware Description Language

Revista EIA ◽  
2020 ◽  
Vol 17 (33) ◽  
Author(s):  
Jorge Hernan Lopez Botero ◽  
Johans Restrepo Cardenas ◽  
Jorge Enrique Tóbon Gómez
Keyword(s):  
Fixed Point ◽  
High Precision ◽  
Hardware Description Language ◽  
Integer Part ◽  
Description Language ◽  
Point Representation ◽  
Hardware Description ◽  
Decimal Numbers ◽  
Gate Array ◽  
Do So

In this work we describe a fast and high-precision algorithm written in VHDL Hardware Description Language to perform the division between two_nite decimal numbers, i.e. numbers composed of an integer part and a decimal one, under the scheme of a fixed point representation. The algorithm proposed is not an approximation one as it is usually considered. To do so, the size of the bits of the operands can be tunned by means of a couple of parameters N and M, according to which the latency of the calculation will depend. The project is _nally sinthesized in a _eld programmable gate array or FPGA of the type SPARTAN 3E from XILINX.

scholarly journals PERANCANGAN DAN IMPLEMENTASI ARSITEKTUR DEMAPPER 64-QAM DI FPGA

2017 ◽  
Author(s):  
Achmad Rizal Mauludin ◽  
Rina Pudji Astuti ◽  
Denny Darlis
Keyword(s):  
High Speed ◽  
Short Message Service ◽  
Hardware Description Language ◽  
Short Message ◽  
Least Significant Bit ◽  
Description Language ◽  
Error Process ◽  
Message Service ◽  
Hardware Description ◽  
Gate Array

Sistem telekomunikasi bertujuan untuk mengirimkan sinyal dari sumber informasi yang dapatberbentuk suara, pesan singkat atau Short Message Service (SMS), gambar, video dan layanan data ke tujuanyang diinginkan. Informasi yang akan dikirimkan akan diubah menjadi sinyal yang dapat dilewati mediatransmisi, dan agar sinyal yang diterima disisi penerima dapat dibaca, diperlukan demodulator yang dapatmengubah sinyal yang diterima menjadi informasi seperti yang dikirimkan. Demodulator 64-QuadratureAmplitude Modulation (QAM) adalah salah satu jenis demodulator yang mampu mendemodulasi sinyalfrekuensi tinggi.Dalam tugas akhir ini, telah dirancang dan diimplementasikan demapper 64-QAM yang merupakansub blok demodulator, pada FPGA (Field Programable Gate Array) yang menggunakan bahasa pengkodeanVery High Speed Integrated Cicuit (VHSIC) Hardware Description Language (VHDL) Fungsi dari blok iniadalah untuk memetakan balik simbol-simbol masukan dengan amplitudo dan fasa yang berbeda-beda yangsebelumnya telah direpresentasikan ke dalam bentuk bit-bit pada sisi pengirim. Pemetaan balik ini mengubahsimbol-simbol tersebut menjadi bit-bit informasi yang masih berupa bit-bit inphase dan quadrature.Dari hasil penelitian ini, untuk kondisi ideal atau gangguan didapatkan output di sisi penerima berupasebuah bit-bit informasi yang sama dengan bit-bit informasi yang dikirimkan pada sisi pengirim. Sedangkanuntuk kondisi ada gangguan, hasil outputnya masih sama dengan bit-bit informasi selama bit yang digangguadalah enam bit dari LSB (Least Significant bit), untuk tujuh bit yang diganggu error process yang terjadiadalah 21,8310 % sedangkan untuk empat belas bit yang diganggu error process yang terjadi sebesar 96,9072%.

The Design of Electronic Code Lock

2011 ◽  
Vol 267 ◽  
pp. 1001-1004
Author(s):  
Si Tong Sun ◽  
An Gang Tian ◽  
De Cai Zhuang
Keyword(s):  
Hardware Description Language ◽  
Description Language ◽  
Top Down ◽  
Hardware Description ◽  
Gate Array

In this paper, by using EDA technology, Quartus II6.0 working platform and VHDL hardware description language, an electronic code lock based on the programmable gate array FPGA is designed with a top-down design.

IP Core Design of 8253 Based on Quartus II

2013 ◽  
Vol 380-384 ◽  
pp. 2941-2944
Author(s):  
Hai Yan Zhang
Keyword(s):  
Software Development ◽  
Hardware Description Language ◽  
Logic Design ◽  
Ip Core ◽  
Description Language ◽  
Development Platform ◽  
Quartus Ii ◽  
Hardware Description ◽  
Gate Array

Provided by ALTERA FPGA/CPLD Quartus II development software development platform. programmable timer/counter 8253s functions and internal circuitry as the basis, combined with programmable gate array (FPGA) products FLEX10KE characteristics, using VHDL hardware description language and schematic Figure two ways 8253 for hierarchical, modular, parameterized logic design. The completed design will be configured to the chip of FLEX10KE,and Proved to be correct.

scholarly journals Detecção de faltas de alta impedância por meio de análise fasorial e correntes de sequência zero

2021 ◽  
Author(s):  
Edson Antonio Batista ◽  
Moacyr Aureliano Gomes Brito ◽  
Renan Saito Kawakita ◽  
Jader Lucas Perez ◽  
Cristiano Quevedo Andrea ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Hardware Description Language ◽  
Description Language ◽  
Matlab Simulink ◽  
Field Programmable ◽  
Hardware Description ◽  
Gate Array

<p class="Normal1"><span>Este trabalho apresenta uma solução para a detecção de faltas de alta impedância (FAIs) usando um dispositivo FPGA <span>(<em>Field Programmable Gate Array</em>). A proposição é de vital importância para o funcionamento adequado do sistema elétrico de distribuição de forma a atender aos requisitos dos procedimentos de distribuição (PRODIST), elaborados pela Agência Nacional de Energia Elétrica (ANEEL). Para analisar o comportamento das grandezas elétricas frente a essa falha, uma rede de distribuição primária foi modelada usando a plataforma MATLAB/Simulink<sup>®</sup>. Paralelamente à modelagem, um algoritmo em linguagem VHDL (VHSIC <em>Hardware Description Language</em>) foi desenvolvido para a detecção da falta, no qual o monitoramento da corrente fasorial por meio da Transformada Discreta de Fourier foi utilizado, além do valor RMS da corrente de sequência zero. Para realizar as simulações e testes do algoritmo, o software ModelSim<sup>®</sup> foi utilizado e, posteriormente, o código foi embarcado no dispositivo de lógica programável FPGA. O algoritmo de detecção de falta de alta impedância foi integrado ao sistema modelado em Simulink<sup>®</sup> para monitoramento em tempo real e comando de um dispositivo de proteção. Os resultados apontam que o algoritmo foi capaz de detectar as faltas, indicando a fase interrompida e comandando a proteção de forma eficiente.</span></span></p>

Random-access memory coding in the Verilog description language for solving problems in radio electronics and mechanical engineering

2021 ◽  
pp. 74-79
Author(s):  
S. S. Yudachev ◽  
S. S. Sitnikov ◽  
P. A. Monakhov
Keyword(s):  
Field Programmable Gate Array ◽  
Random Access ◽  
Random Access Memory ◽  
Hardware Description Language ◽  
Description Language ◽  
Access Memory ◽  
Field Programmable ◽  
Hardware Description ◽  
Gate Array ◽  
Verilog Hardware Description Language

The article proposes a variant of writing an algorithm for the operation of a device used in a field-programmable gate array on the example of random-access memory coding using the Verilog hardware description language. When performing the work, the Xilinx software is used, which allows working with the project at all stages of creating and describing the operation of the device logic. The practical significance of the work is the study and solution of the simplest problems in the development of modern radioelectronic rapid response devices in the Verilog hardware description language, such as coding a field-programmable gate array itself, writing test debugging code, setting input and output signals, sync pulse, reset and enable signals, describing the logic of devices such as counters, switches, registers and triggers, as well as simulating a finished project to assess the correct operation of the programmed device. This work can be used not only for teaching students of higher educational institutions in the field of development, debugging and coding of electronic and radio-electronic devices in terms of describing the algorithm of their work, but also for organizing laboratory work on courses of disciplines related to this topic, and for creating and designing real devices in production. The introduction and study of this programming language are conducted within the walls of one of the leading engineering universities of the Russian Federation — the Bauman Moscow State Technical University.

Efficient Conversion Technique from Redundant Binary to NonRedundant Binary Representation

2017 ◽  
Vol 26 (09) ◽  
pp. 1750135 ◽  
Author(s):  
Ranjan Kumar Barik ◽  
Manoranjan Pradhan ◽  
Rutuparna Panda
Keyword(s):  
Final Stage ◽  
Hardware Description Language ◽  
Binary Representation ◽  
Description Language ◽  
Power Product ◽  
Efficient Conversion ◽  
Look Ahead ◽  
Hardware Description ◽  
Sign Extension ◽  
Cadence Tool

Redundant Binary (RB) to Two’s Complement (TC) converter offers nonredundant representation. However, the sign bit of TC representation has to be handled using nonstandard hardware blocks. The concept of Inverted encoding of negative weighted bits (IEN) eliminates the need of sign extension and offers design only using predefined hardware blocks. NonRedundant Binary (NRB) representation refers to both conventional and IEN representations. The NRB representation is also useful considering problem related to shifting in Carry Save (CS) representation of a RB number. In this paper, we have proposed two new conversion circuits for RB to NRB representation. The proposed circuits of the RB to NRB converter are coded in Verilog Hardware Description language (HDL) and synthesized using the Encounter(R) RTL Compiler RC13.10 v13.10-s006_1 of Cadence tool considering ASIC platform. Considering 64 bits’ operand, the delay power product performances of proposed one-bit and two-bit computations offer improvement of almost 29.9% and 47%, respectively as compared to Carry-Look-Ahead (CLA). The proposed one-bit converter is also applied in the final stage of the Modified Redundant Binary Adder (MRBA). The 32-bit MRBA offers a delay improvement of 7.87% replacing conventional converter with proposed one-bit converter in same FPGA 4vfx12sf363-12 device.

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