scholarly journals Detecção de faltas de alta impedância por meio de análise fasorial e correntes de sequência zero

2021 ◽  
Author(s):  
Edson Antonio Batista ◽  
Moacyr Aureliano Gomes Brito ◽  
Renan Saito Kawakita ◽  
Jader Lucas Perez ◽  
Cristiano Quevedo Andrea ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Hardware Description Language ◽  
Description Language ◽  
Matlab Simulink ◽  
Field Programmable ◽  
Hardware Description ◽  
Gate Array

<p class="Normal1"><span>Este trabalho apresenta uma solução para a detecção de faltas de alta impedância (FAIs) usando um dispositivo FPGA <span>(<em>Field Programmable Gate Array</em>). A proposição é de vital importância para o funcionamento adequado do sistema elétrico de distribuição de forma a atender aos requisitos dos procedimentos de distribuição (PRODIST), elaborados pela Agência Nacional de Energia Elétrica (ANEEL). Para analisar o comportamento das grandezas elétricas frente a essa falha, uma rede de distribuição primária foi modelada usando a plataforma MATLAB/Simulink<sup>®</sup>. Paralelamente à modelagem, um algoritmo em linguagem VHDL (VHSIC <em>Hardware Description Language</em>) foi desenvolvido para a detecção da falta, no qual o monitoramento da corrente fasorial por meio da Transformada Discreta de Fourier foi utilizado, além do valor RMS da corrente de sequência zero. Para realizar as simulações e testes do algoritmo, o software ModelSim<sup>®</sup> foi utilizado e, posteriormente, o código foi embarcado no dispositivo de lógica programável FPGA. O algoritmo de detecção de falta de alta impedância foi integrado ao sistema modelado em Simulink<sup>®</sup> para monitoramento em tempo real e comando de um dispositivo de proteção. Os resultados apontam que o algoritmo foi capaz de detectar as faltas, indicando a fase interrompida e comandando a proteção de forma eficiente.</span></span></p>

Random-access memory coding in the Verilog description language for solving problems in radio electronics and mechanical engineering

2021 ◽  
pp. 74-79
Author(s):  
S. S. Yudachev ◽  
S. S. Sitnikov ◽  
P. A. Monakhov
Keyword(s):  
Field Programmable Gate Array ◽  
Random Access ◽  
Random Access Memory ◽  
Hardware Description Language ◽  
Description Language ◽  
Access Memory ◽  
Field Programmable ◽  
Hardware Description ◽  
Gate Array ◽  
Verilog Hardware Description Language

The article proposes a variant of writing an algorithm for the operation of a device used in a field-programmable gate array on the example of random-access memory coding using the Verilog hardware description language. When performing the work, the Xilinx software is used, which allows working with the project at all stages of creating and describing the operation of the device logic. The practical significance of the work is the study and solution of the simplest problems in the development of modern radioelectronic rapid response devices in the Verilog hardware description language, such as coding a field-programmable gate array itself, writing test debugging code, setting input and output signals, sync pulse, reset and enable signals, describing the logic of devices such as counters, switches, registers and triggers, as well as simulating a finished project to assess the correct operation of the programmed device. This work can be used not only for teaching students of higher educational institutions in the field of development, debugging and coding of electronic and radio-electronic devices in terms of describing the algorithm of their work, but also for organizing laboratory work on courses of disciplines related to this topic, and for creating and designing real devices in production. The introduction and study of this programming language are conducted within the walls of one of the leading engineering universities of the Russian Federation — the Bauman Moscow State Technical University.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals Simple Hardware Implementation of Motion Estimation Algorithms

2019 ◽  
Vol 11 (3) ◽  
Author(s):  
Juan Romero ◽  
Damien Verdier ◽  
Clement Raffaitin ◽  
Luis Miguel Procel ◽  
Lionel Trojman
Keyword(s):  
Optical Flow ◽  
Field Programmable Gate Array ◽  
Hardware Implementation ◽  
Software Implementation ◽  
Hardware Description Language ◽  
Successful Implementation ◽  
Description Language ◽  
Estimation Algorithms ◽  
Field Programmable ◽  
Hardware Description

We present in the following work a hardware implementation of the two principal optical flow methods. The work is based on the methods developed by Lucas & Kanade, and Horn & Schunck. The implementation is made by using a field programmable gate array and Hardware Description Language. To achieve a successful implementation, the algorithms were optimized. The results show the optical flow as a vector field over one frame, which enable an easy detection of the movement. The results are compared to a software implementation to insure the success of the method. The implementation is a fast implementation capable of quickly overcoming a traditional implementation in software.

scholarly journals Support Vector Machine working on FPGA and the segmentation method of brain MR screening

2017 ◽  
Vol 4 (3) ◽  
pp. 120 ◽  
Author(s):  
Fatih Şişik ◽  
Eser Sert
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Support Vector ◽  
Segmentation Method ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Very High

Alan Programlanabilir Kapı Dizileri (Field Programmable Gate Array-FPGA) programlanabilir sayısal bloklar ve bağlantılarını içeren cihazlar olup çok esnek ve hızlı çalışabilme özelliklerine sahiptir. Programlanabilen bu sayısal kapılar sayesinde karmaşık tasarımlar kolay bir şekilde geliştirilebilmektedir. FPGA’lar küçük boyutlarda olup bilgisayardan bağımsız mobil olarak ve bilgisayarlardan daha yüksek hızlarda çalışabilmektedirler. Veri madenciliğinin görevlerinden biri olan sınıflandırma probleminin çözümü için geliştirilmiş önemli makine öğrenimi algoritmalarından biri Destek Vektör Makineleri’ dir. Literatürde Destek Vektör Makineleri’ nin diğer birçok tekniğe göre daha başarılı sonuçlar verdiği kanıtlanmıştır. Tümör analizi, yüz tanıma, robotik göz oluşturma gibi konular, araştırmacıların görüntü işleme alanında yoğun olarak üzerinde çalıştıkları güncel, önemli ve zor problemlerden bazılarıdır. Bilgisayarda yapılan tümör analizinde, grafik ve resimlerin işlenmesinde yavaş işlem yapma ve aynı zamanda mobil olmama sorunlarından, FPGA donanımı ile görüntü işlemede bu sorunların üstesinden gelinmektedir. Bu çalışmada FPGA donanımında çalışan destek vektör makinası kullanılarak daha gerçekçi tümör analizi yapılarak tümörlü bölgelerin bulunması ve gerekli analiz sonuçlarının gösterilmesi amaçlanmaktadır. Böylece sağlık alanında da kullanılabilecek yararlı bir donanımın tasarımı gerçekleştirilecektir. Dolayısıyla gömülü sistemlerle anlatılan bu işlem süreçlerini gerçekleştiren çalışma sayısı çok az olduğundan çalışma özgün değer taşımaktadır. Buna ek olarak, FPGA’ ya özgü donanım tanımlama dillerinden biri olan Çok Yüksek Hızlı Tümleşik Devre Tanımlama Dili (Very High Speed Integrated Circuit  Hardware Description Language- VHDL) kullanılacaktır. Bölütleme sonucunun değerlendirilmesi için Uniformity Measure (UM) kullanılmıştır. UM değerlendirme sonucunun başarılı olduğu görülmüştür. Anahtar Kelimeler: Alan Programlanabilir Kapı Dizileri, FPGA, çok yüksek hızlı tümleşik devre tanımlama dili, vhdl, segmentasyon, destek vektör makinesi

Implementation Study Of Field Programmable Gate Array (FPGA) And Complex Programmable Logic Device (CPLD) In Collision Avoidance System Using Vhsic Hardware Description Language (VHDL)

Mekatronika ◽  
2021 ◽  
Vol 3 (1) ◽  
pp. 52-60
Author(s):  
Mohammad Naqiuddin Fahmi Fathli ◽  
Zulkifli Md Yusof
Keyword(s):  
Collision Avoidance ◽  
Field Programmable Gate Array ◽  
Hardware Description Language ◽  
Programmable Logic ◽  
Logic Device ◽  
Description Language ◽  
Field Programmable ◽  
Hardware Description ◽  
Complex Programmable Logic Device ◽  
Collision Avoidance System

A collision avoidance system, also known as a pre-crash system, forward collision warning system, or collision mitigation system, is a sophisticated driver-assistance system that aims to avoid or mitigate the severity of a collision. For this research, collision avoidance system will be fabricating to show that this system can detect avoidance range before apply the braking action to prevent collision. The ultrasonic sensor will be used in this system to detect the avoidance range. In this collision avoidance system, there will be uses of Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD). This research will observe how to implement FPGA and CPLD in the collision avoidance system using VHSIC Hardware Description Language (VHDL). The VHDL will be done in Quartus II 15.0 Software. In this research, Terasic DE-10 Standard board has been used. It contains FPGA microcontroller model Cyclone V SoC 5CSXFC6D6F31C6N. Max II board is used because it contains CPLD microcontroller model EPM240T100C5.

scholarly journals PERANCANGAN DAN IMPLEMENTASI ARSITEKTUR DEMAPPER 64-QAM DI FPGA

2017 ◽  
Author(s):  
Achmad Rizal Mauludin ◽  
Rina Pudji Astuti ◽  
Denny Darlis
Keyword(s):  
High Speed ◽  
Short Message Service ◽  
Hardware Description Language ◽  
Short Message ◽  
Least Significant Bit ◽  
Description Language ◽  
Error Process ◽  
Message Service ◽  
Hardware Description ◽  
Gate Array

Sistem telekomunikasi bertujuan untuk mengirimkan sinyal dari sumber informasi yang dapatberbentuk suara, pesan singkat atau Short Message Service (SMS), gambar, video dan layanan data ke tujuanyang diinginkan. Informasi yang akan dikirimkan akan diubah menjadi sinyal yang dapat dilewati mediatransmisi, dan agar sinyal yang diterima disisi penerima dapat dibaca, diperlukan demodulator yang dapatmengubah sinyal yang diterima menjadi informasi seperti yang dikirimkan. Demodulator 64-QuadratureAmplitude Modulation (QAM) adalah salah satu jenis demodulator yang mampu mendemodulasi sinyalfrekuensi tinggi.Dalam tugas akhir ini, telah dirancang dan diimplementasikan demapper 64-QAM yang merupakansub blok demodulator, pada FPGA (Field Programable Gate Array) yang menggunakan bahasa pengkodeanVery High Speed Integrated Cicuit (VHSIC) Hardware Description Language (VHDL) Fungsi dari blok iniadalah untuk memetakan balik simbol-simbol masukan dengan amplitudo dan fasa yang berbeda-beda yangsebelumnya telah direpresentasikan ke dalam bentuk bit-bit pada sisi pengirim. Pemetaan balik ini mengubahsimbol-simbol tersebut menjadi bit-bit informasi yang masih berupa bit-bit inphase dan quadrature.Dari hasil penelitian ini, untuk kondisi ideal atau gangguan didapatkan output di sisi penerima berupasebuah bit-bit informasi yang sama dengan bit-bit informasi yang dikirimkan pada sisi pengirim. Sedangkanuntuk kondisi ada gangguan, hasil outputnya masih sama dengan bit-bit informasi selama bit yang digangguadalah enam bit dari LSB (Least Significant bit), untuk tujuh bit yang diganggu error process yang terjadiadalah 21,8310 % sedangkan untuk empat belas bit yang diganggu error process yang terjadi sebesar 96,9072%.

scholarly journals A Real Time Algorithm for Versatile Mode Parking System and Its Implementation on FPGA Board

2022 ◽  
Vol 12 (2) ◽  
pp. 655
Author(s):  
Baligh Naji ◽  
Chokri Abdelmoula ◽  
Mohamed Masmoudi
Keyword(s):  
Real Time ◽  
Evaluation Process ◽  
Time Algorithm ◽  
Hardware Description Language ◽  
Optimal Solutions ◽  
Description Language ◽  
Parking System ◽  
Parking Lot ◽  
Field Programmable ◽  
Hardware Description

This paper presents the design and development of a technique for an Autonomous and Versatile mode Parking System (AVPS) that combines a various number of parking modes. The proposed approach is different from that of many developed parking systems. Previous research has focused on choosing only a parking lot starting from two parking modes (which are parallel and perpendicular). This research aims at developing a parking system that automatically chooses a parking lot starting from four parking modes. The automatic AVPS was proposed for the car-parking control problem, and could be potentially exploited for future vehicle generation. A specific mode can be easily computed using the proposed strategy. A variety of candidate modes could be generated using one developed real time VHDL (VHSIC Hardware Description Language) algorithm providing optimal solutions with performance measures. Based on simulation and experimental results, the AVPS is able to find and recognize in advance which parking mode to select. This combination describes full implementation on a mobile robot, such as a car, based on a specific FPGA (Field-Programmable Gate Array) card. To prove the effectiveness of the proposed innovation, an evaluation process comparing the proposed technique with existing techniques was conducted and outlined.

FPGA-BASED MOTION CONTROLLER FOR WAFER-HANDLING ROBOT

2013 ◽  
Vol 37 (3) ◽  
pp. 427-437
Author(s):  
Hsin-Hung Chou ◽  
Ying-Shieh Kung ◽  
Tai-Wei Tsui ◽  
Stone Cheng
Keyword(s):  
Hardware Description Language ◽  
Motion Controller ◽  
Description Language ◽  
Gate Arrays ◽  
Current Vector ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Axis Position ◽  
Hardware Description ◽  
Fpga Chip

This study applies FPGA (Field Programmable Gate Arrays) technology to implement a motion controller for wafer-handling robot which has three-DOF (Degree of Freedom) motion. The proposed FPGA-based motion controller has two modules. The first module is Nios II processor which is used to realize the motion trajectory computation and the three-axis position/speed controllers. The second module is demonstrated to implement the three-axis current vector controllers by using FPGA hardware, and VHDL (VHSIC Hardware Description Language) is adopted to describe the controller behavior. Therefore, a fully digital motion controller for wafer-handling robot, such as one trajectory planning, three current vector controllers and three position/speed controllers are all implemented with an FPGA chip.

scholarly journals Gait Control of Hexapod Robot Based on Field-Programmable Gate Array and Central Pattern Generator

2020 ◽  
Vol 53 (6) ◽  
pp. 931-937
Author(s):  
Tianbo Qiao
Keyword(s):  
Central Pattern Generator ◽  
Field Programmable Gate Array ◽  
Control Method ◽  
Pattern Generator ◽  
Hexapod Robot ◽  
Gait Control ◽  
Field Programmable ◽  
Physical Prototype ◽  
Hardware Description ◽  
Gate Array

This paper attempts to improve the terrain adaptability of hexapod robot through gait control. Firstly, the multi-leg coupling in the tripodal gait of the hexapod robot was modeled by Hopf oscillator. Then, annular central pattern generator (CPG) was adopted to simulate the leg movements of hexapod robot between signals. Furthermore, a physical prototype was designed for the gait control test on field-programmable gate array (FPGA), and the algorithm of the rhythmic output of the model was programmed in Verilog, a hardware description language. Finally, the effectiveness of our gait control method was verified through the simulation on Xilinx. The results show that the phase difference of the CPG network remained stable; the designed hexapod robot moved at about 5.15cm/s stably in a tripodal gait, and outperformed wheeled and tracked robots in terrain adaptation. The research findings lay a solid basis for the design of all-terrain multi-leg robots.

The Design of Electronic Code Lock

2011 ◽  
Vol 267 ◽  
pp. 1001-1004
Author(s):  
Si Tong Sun ◽  
An Gang Tian ◽  
De Cai Zhuang
Keyword(s):  
Hardware Description Language ◽  
Description Language ◽  
Top Down ◽  
Hardware Description ◽  
Gate Array

In this paper, by using EDA technology, Quartus II6.0 working platform and VHDL hardware description language, an electronic code lock based on the programmable gate array FPGA is designed with a top-down design.

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