Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

scholarly journals Reduction in the number of LUT elements for control units with code sharing

2010 ◽  
Vol 20 (4) ◽  
pp. 751-761 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Jacek Bieganowski
Keyword(s):  
Field Programmable Gate Arrays ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Control Units ◽  
Linear Chains ◽  
Code Sharing ◽  
Field Programmable ◽  
Programmable Gate Arrays

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs

2019 ◽  
Vol 28 (08) ◽  
pp. 1950131 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski
Keyword(s):  
Formal Method ◽  
Field Programmable Gate Arrays ◽  
Finite State Machines ◽  
Logic Circuits ◽  
State Machines ◽  
Gate Arrays ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays

A method is proposed targeting the decrease of the number of look-up tables (LUTs) in logic circuits of field programmable gate arrays (FPGA)-based Mealy finite state machines. The method is based on constructing a partition for the set of output variables. It diminishes the number of additional variables encoding the collections of output variables (COVs). A formal method is proposed for finding the partition. An example of synthesis is given, as well as the results of investigations. The investigations were conducted for standard benchmarks.

scholarly journals RISC Conversions for LNS Arithmetic in Embedded Systems

Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1208 ◽  
Author(s):  
Peter Drahoš ◽  
Michal Kocúr ◽  
Oto Haffner ◽  
Erik Kučera ◽  
Alena Kozáková
Keyword(s):  
Embedded Systems ◽  
Number System ◽  
Real Time Control ◽  
Gate Arrays ◽  
Time Control ◽  
Camera Systems ◽  
Control Units ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Logarithmic Number

The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP) representations named “looping in sectors”, which brings about reduced memory consumption without a loss of accuracy. The resulting effective RISC conversions use only elementary computer operations without the need to employ multiplication, division, or other functions. Verification of the new concept and related developed algorithms for conversion between the LNS and the FLP representations was realized on Field Programmable Gate Arrays (FPGA), and the conversion accuracy was evaluated via simulation. Using the proposed method, a maximum relative conversion error of less than ±0.001% was achieved with a 22-ns delay and a total of 50 slices of FPGA consumed including memory cells. Promising applications of the proposed method are in embedded systems that are expanding into increasingly demanding applications, such as camera systems, lidars and 2D/3D image processing, neural networks, car control units, autonomous control systems that require more computing power, etc. In embedded systems for real-time control, the developed conversion algorithm can appear in two forms: as RISC conversions or as a simple RISC-based logarithmic addition.

Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations

2015 ◽  
Vol 24 (03) ◽  
pp. 1550039 ◽  
Author(s):  
Grace Zgheib ◽  
Iyad Ouaiss
Keyword(s):  
State Of The Art ◽  
Variable Structure ◽  
Logic Circuits ◽  
Technology Mapping ◽  
Decomposition Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Boolean Matching ◽  
Programmable Gate Arrays ◽  
Logic Functions

In the state-of-the-art field-programmable gate arrays (FPGAs), logic circuits are synthesized and mapped on clusters of look-up tables. However, arithmetic operations benefit from an existing dedicated adder along with a carry chain used to ensure a fast carry propagation. This carry chain is a dedicated wire available in the architecture of the FPGA and is as such independent of the external programmable routing resources. In this paper, we propose a variable-structure Boolean matching technology mapper with embedded decomposition techniques to map nonarithmetic logic functions on carry chains. Previously synthesized and mapped logic functions are adapted so that their outputs are routed using the dedicated carry chains instead of the external programmable interconnects. The experimental results show a reduction in the used routing resources as well as the circuit area when using this Boolean matching-based mapper on the Altera Stratix-III FPGA.

scholarly journals Reconfigurable, Multi-channel and Modular Bioimpedance Spectroscopy System on Field Programmable Gate Arrays

2017 ◽  
Author(s):  
Anis Nurashikin Nordin ◽  
Ahmed Al-Hashimi ◽  
Amelia Wong Azman
Keyword(s):  
Flash Memory ◽  
Control Unit ◽  
Field Programmable Gate Arrays ◽  
Device Under Test ◽  
Gate Arrays ◽  
Final Data ◽  
Balance Bridge ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Spectroscopy System

This paper presents the design and implementation of a multichannel bio-impedance spectroscopy system on field programmable gate arrays (FPGA). The proposed system is capable of acquiring multiple signals from multiple bio-impedance sensors, process the data on the FPGA and store the final data in the on-board Memory. The system employs the Digital Automatic Balance Bridge (DABB) method to acquire data from biosensors. The DABB measures initial data of a known impedance to extrapolate the value of the impedance for the device under test. This method offers a simpler design because the balancing of the circuit is done digitally in the FPGA rather than using an external circuit. Calculations of the impedance values for the device under test were done in the processor. The final data is sent to an onboard Flash Memory to be stored for later access. The control unit handles the interfacing and the scheduling between these different modules (Processor, Flash Memory) as well as interfacing to multiple Balance Bridge and multiple biosensors. The system has been simulated successfully and has comparable performance to other FPGA based solutions. The system has a robust design that is capable of handling and interfacing input from multiple biosensors. Data processing and storage is also performed with minimal resources on the FPGA.

scholarly journals On the Power Dissipation of Embedded Memory Blocks Used to Implement Logic in Field-Programmable Gate Arrays

2008 ◽  
Vol 2008 ◽  
pp. 1-13 ◽  
Author(s):  
Scott Y. L. Chin ◽  
Clarence S. P. Lee ◽  
Steven J. E. Wilton
Keyword(s):  
Power Consumption ◽  
Power Dissipation ◽  
Embedded Memory ◽  
Power Efficient ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Power And Energy ◽  
Embedded Memories ◽  
The Impact

We investigate the power and energy implications of using embedded FPGA memory blocks to implement logic. Previous studies have shown that this technique provides extremely dense implementations of some types of logic circuits, however, these previous studies did not evaluate the impact on power. In this paper, we measure the effects on power and energy as a function of three architectural parameters: the number of available memory blocks, the size of the memory blocks, and the flexibility of the memory blocks. We show that although embedded memories provide area efficient implementations of many circuits, this technique results in additional power consumption. We also show that blocks containing smaller-memory arrays are more power efficient than those containing large arrays, but for most array sizes, the memory blocks should be as flexible as possible. Finally, we show that by combining physical arrays into larger logical memories, and mapping logic in such a way that some physical arrays can be disabled on each access, can reduce the power consumption penalty. The results were obtained from place and routed circuits using standard experimental physical design tools and a detailed power model. Several results were also verified through current measurements on a 0.13 μm CMOS FPGA.

scholarly journals Identify a Spoofing Attack on an In-Vehicle CAN Bus Based on the Deep Features of an ECU Fingerprint Signal

Smart Cities ◽  
2020 ◽  
Vol 3 (1) ◽  
pp. 17-30
Author(s):  
Yun Yang ◽  
Zongtao Duan ◽  
Mark Tehranipoor
Keyword(s):  
Autonomous Vehicles ◽  
Short Term Memory ◽  
Can Bus ◽  
Area Network ◽  
Gate Arrays ◽  
Control Units ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Long Short Term Memory ◽  
High Computational Complexity

An in-vehicle controller area network (CAN) bus is vulnerable because of increased sharing among modern autonomous vehicles and the weak protocol design principle. Spoofing attacks on a CAN bus can be difficult to detect and have the potential to enable devastating attacks. To effectively identify spoofing attacks, we propose the authentication of sender identities using a recurrent neural network with long short-term memory units (RNN-LSTM) based on the features of a fingerprint signal. We also present a way to generate the analog fingerprint signals of electronic control units (ECUs) to train the proposed RNN-LSTM classifier. The proposed RNN-LSTM model is accelerated on embedded Field-Programmable Gate Arrays (FPGA) to allow for real-time detection despite high computational complexity. A comparison of experimental results with the latest studies demonstrates the capability of the proposed RNN-LSTM model and its potential as a solution to in-vehicle CAN bus security.

scholarly journals FPGA Technology and Sequential Finite State Machine Method

2018 ◽  
Vol 127 (1D) ◽  
pp. 55
Author(s):  
Nguyen Khanh Quang ◽  
Nguyen Ho Quang
Keyword(s):  
Finite State Machine ◽  
Design Method ◽  
State Machine ◽  
Machine Method ◽  
Gate Arrays ◽  
Design Engineers ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Basic Level

<em>The implementation of complex control algorithms on an FPGA</em> (Field programmable gate arrays)<em> is still at a basic level. There is no fixed method to develop algorithms on these devices because of their general characteristics. Therefore, the design engineers are still on the way to find the good approaches to optimize the implementation of algorithms on FPGAs [1-7]. This paper presents and demonstrates a sequential finite state machine design method that can solve the issue of optimal usage of the limited resources on an FPGA.</em>

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