scholarly journals CMOS Image Sensor Featuring Current-Mode Focal-Plane Image Compression

2013 ◽  
Vol 8 (1) ◽  
pp. 14-21
Author(s):  
Fernanda D. V. R. Oliveira ◽  
Hugo L. Haas ◽  
José Gabriel R. C. Gomes ◽  
Antonio Petraglia
Keyword(s):  
Image Compression ◽  
Focal Plane ◽  
High Speed ◽  
Low Voltage ◽  
Current Mode ◽  
Image Sensor ◽  
Cmos Process ◽  
Target Pattern ◽  
Differential Pulse Code Modulation ◽  
Plane Image

The interest in focal-plane processing techniques, by which image processing is carried out at the pixel level, has increased since the advent of active pixel sensors in the middle 90’s. By sharing processing circuitry by a group of neighboring pixels such techniques enable high-speed imaging operation and massive parallel computation. Focal-plane image compression is particularly interesting, because it allows for further reduction in data rates. The proposed approach also benefits from processing currents rather than voltages, which not only suits current-mode APS imagers, but also enables the circuits to operate at low voltage supply levels and achieve high speed. Moreover, arithmetic computations such as additions and scaling are easily implemented in current mode. Whereas current-mode imaging architectures produce higher fixed pattern noise (FPN) figures than their voltage-mode counterparts, low FPN can be achieved by applying correlated double sampling (CDS) and gain correction techniques. This work presents a 32 × 32 gray-level imaging integrated circuit featuring focal plane image compression, such that for each 4 × 4 pixel block, analog circuits implement differential pulse-code modulation, linear transform, and vector quantization. Other processing functions implemented in the chip are CDS and A/D conversion. Theoretical details are described, as well as the test setup of the chip fabricated in a 0.35 μm CMOS process. To validate the proposed technique, experimental results and captured photographs are shown. The CMOS imager compresses captured images at 0.94 bits/pixel for an overall power consumption below 40 mW (white image), which is equivalent to approximately 36 μW per pixel. Using photographs taken from bar-target pattern inputs, it is shown that details up to 2 cycles/c mare preserved in the decoded images.

scholarly journals Focal-Plane Compression Imager with Increased Quantization Bit Rate and DPCM Error Modeling

2017 ◽  
Vol 12 (2) ◽  
pp. 71-81
Author(s):  
Fernanda Duarte Vilela Reis De Oliveira ◽  
Tiago Monnerat de Faria Lopes ◽  
José Gabriel Rodríguez Carneiro Gomes ◽  
Fernado Antônio Pinto Barúqui ◽  
Antonio Petraglia
Keyword(s):  
Focal Plane ◽  
Second Generation ◽  
Vision System ◽  
Image Sensor ◽  
Error Modeling ◽  
Cmos Process ◽  
Differential Pulse Code Modulation ◽  
Current Mirrors ◽  
Linear Transform ◽  
Focal Plane Processing

Focal-plane processing is the target of many studies due to its potential for enhancing the speed of the vision system flow. With focal-plane processing it is possible to perform parallel processing throughout the entire matrix. In order to alleviate A/D conversion and transmission constraints, analog image compression is implemented at the focal plane, thereby reducing the amount of data to be transmitted and the bandwidth requirements. The ADC is performed at the focal plane as well, after the compression operation whose realization is based on differential pulse-code modulation (DPCM), linear transform and vector quantization (VQ) applied on every 4 × 4 pixel block using current-mode circuits. This paper presents experimental results obtained from a second-generation version of the image sensor. Among these results we can point out the presentation of different captured images and the modeling of errors that were identified during the experimental tests. Since the source of these errors is the DPCM stage, the modeling concerns the bits that refer to the mean block luminance results. The error modeling procedure was developed considering the relationship between the pixel integration period and the DPCM quantizer threshold values. The main contributions of the second-generation chip in comparison to the previous realization are: increase of the vector quantizer complexity, number of bits per pixel, pixel matrix size, and the use of cascode current mirrors in the linear transform matrix. The image sensor advanced in this paper was fabricated in a standard 180 nm CMOS process.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

CCD focal-plane image reorganization processors for lossless image compression

1992 ◽  
Vol 27 (3) ◽  
pp. 398-405 ◽  
Author(s):  
S.E. Kemeny ◽  
H.H. Torbey ◽  
H.E. Meadows ◽  
R.A. Bredthauer ◽  
M.A. La Shell ◽  
...  
Keyword(s):  
Image Compression ◽  
Focal Plane ◽  
Lossless Image Compression ◽  
Plane Image

High Speed Min/Max Architecture Based on a Novel Comparator in 0.18-μm CMOS Process

2015 ◽  
Vol 24 (04) ◽  
pp. 1550048 ◽  
Author(s):  
Amir Fathi ◽  
Abdollah Khoei ◽  
Khayrollah Hadidi
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Current Mode ◽  
Cmos Technology ◽  
Operating Frequency ◽  
Cmos Process ◽  
Fuzzy Logic Controllers ◽  
Speed Performance ◽  
External Clock ◽  
Frequency Feature

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology.

scholarly journals A low-voltage CMOS current-mode incremental signaling scheme for high-speed parallel links

2021 ◽  
Author(s):  
Tao Wang
Keyword(s):  
High Speed ◽  
Low Voltage ◽  
Low Cost ◽  
Current Mode ◽  
Cmos Technology ◽  
Fully Differential ◽  
Parallel Links ◽  
Data Links ◽  
Parallel Data ◽  
The Cost

Point-to-point parallel links are widly used in short-distance high-speed data communications. For these links, the design goal is not only to integrate a large number of I/Os in the systems, but also to increase the bit rate per I/O. The cost per I/O has to be kept low as performance improves. Voltage and timing error sources limit the performance of data links and affect its robustnest. These kinds of noise impose greater challenges in parallel data links, such as inter-signal timing skew and inter-signal cross-talk. The use of low-cost schemes, such as single-ended signaling, is effected signaficantly [sic] by the voltage and timging [sic] noise. Fully differential signaling schemes, two physical paths per signal channel, significantly increases the cost of system. Therefore, overcoming the voltage noise, keeping the cost low are two challenges in high-speed parallel links. In this thesis, we propose a new current-mode signaling scheme current-mode incremtnal [sic] signaling for high-speed parallel links. Also, the circuits of the receiver called current-integrating receiver are presented. To assess the effectiveness of the proposed signaling scheme, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10 cm microstrip lines with a FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13[micro]m, 1.2V CMOS technology and analyzed using SpectreRF from Cadence Design Systems with BSIM3V3 device models. Simulation results demonstrate that the proposed current-mode incremental signaling scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 Gbyte/s.

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