scholarly journals Investigation into Class E/F3 with Parallel Network

Radiotekhnika ◽  
2021 ◽  
pp. 120-127
Author(s):  
D.G. Makarov ◽  
D.V. Chernov ◽  
V.V. Kryzhanovskyi ◽  
Yu.V. Rassokhina ◽  
V.G. Kryzhanovskyi ◽  
...  
Keyword(s):  
Harmonic Balance ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Duty Ratio ◽  
System Of Equations ◽  
Drain Voltage ◽  
Amplifier Output ◽  
Harmonic Filter ◽  
Parallel Network ◽  
Class E

The system of equations for processes in the amplifier output network is analytically formulated. This system of equations considers parameters of resonant networks at higher harmonics. To calculate amplifier output network, the system of five equations was built for five unknowns, to which the condition of positive second voltage derivative at extremum of drain voltage was added. Two equations correspond to class E conditions, another two — quadrature waveforms at load and at additional resonant network. The last equation is the condition of extremum at the point near middle of drain voltage pulse. This system was solved using computer algebra program. The circuit elements and waveforms were calculated using the derived parameters. By choosing different parameters, it is possible to obtain various amplifier realizations, which will demonstrate features of different class F variants. The obtained amplifier parameters drain voltage and current waveforms were verified with calculated ones using the harmonic balance simulating software. The variant, which is closer to class E/F3 mode, was chosen to build an experimental amplifier prototype on frequency 2MHz using IRF530 MOSFET as a switch. The prototype was tested in the range of supply dc voltage up to 24V with the output power greater than 6W, while the amplifier efficiency was >80%. In the experiment, the ratio of peak drain voltage to dc supply voltage was measured to be 3.3 at the duty ratio 50%, unlike class E amplifier, where this value is around 3.65, and on practice, considering non-linear drain to source capacitance, it may achieve 4. The experimental second harmonic level amounted to be -20 dB relatively to fundamental, and the third one — 28.5 dB, which is due to an additional second harmonic filter. The paper results are useful for introduction of such circuits to practice.

scholarly journals Design of 2MHz OOK transmitter/receiver for inductive power and data transmission for biomedical implant

2019 ◽  
Vol 9 (4) ◽  
pp. 2779 ◽  
Author(s):  
Abdelali El Boutahiri ◽  
Mounir Ouremchi ◽  
Ahmed Rahali ◽  
Mustapha El Alaoui ◽  
Fouad Farah ◽  
...  
Keyword(s):  
Data Transmission ◽  
Supply Voltage ◽  
Receiver Coil ◽  
Cmos Process ◽  
Power Transfer ◽  
Biomedical Implant ◽  
Transmitter Coil ◽  
Implant System ◽  
Inductive Power ◽  
Class E

<p>In this work a 2 MHz on-off keying (OOK) transmitter/receiver for inductive power and data transmission for biomedical implant system is presented. Inductive link, driven by a Class E power amplifier (PA) is the most PA used to transfer data and power to the internal part of biomedical implant system. Proposed transmitter consists of a digital control oscillator (DCO) and a class E PA which uses OOK modulation to transfer both data and power to a biomedical implant. In proposing OOK transmitter when the transmitter sends binary value “0” the DCO and PA are turned off. With this architecture and 2 MHz carrier wave we have implemented a wireless data and power transfer link which can transmit data with data rate 1Mbps and bit error rate (BER) of 10-5. The efficiency of power transfer is 42% with a 12.7 uH transmitter coil and a 2.4 uH receiver coil and the power delivered to the load is about 104.7 mW. Proposed transmitter is designed for output power 4.1V. OOK receiver consists of an OOK demodulator, powered by rectified and regulated 5V p-p RF signal across the receiver coil. The supply voltage of proposed voltage regulator is 5 V with 9mV/V line regulation of. All circuits proposed in this paper were designed and simulated using Cadence in 0.18 um CMOS process.</p>

scholarly journals A 350-GHz Coupled Stack Oscillator with −0.8 dBm Output Power in 65-nm Bulk CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (8) ◽  
pp. 1214
Author(s):  
Thanh Dat Nguyen ◽  
Jong-Phil Hong
Keyword(s):  
Output Power ◽  
Supply Voltage ◽  
Second Harmonic ◽  
Power Level ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Output Power Level ◽  
Cmos Process ◽  
Frequency Selective ◽  
Oscillation Frequencies

This paper presents a push-push coupled stack oscillator that achieves a high output power level at terahertz (THz) wave frequency. The proposed stack oscillator core adopts a frequency selective negative resistance topology to improve negative transconductance at the fundamental frequency and a transformer connected between gate and drain terminals of cross pair transistors to minimize the power loss at the second harmonic frequency. Next, the phases and the oscillation frequencies between the oscillator cores are locked by employing an inductor of frequency selective negative resistance topology. The proposed topology was implemented in a 65-nm bulk CMOS technology. The highest measured output power is −0.8 dBm at 353.2 GHz while dissipating 205 mW from a 2.8 V supply voltage.

scholarly journals Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

2009 ◽  
Vol 2009 ◽  
pp. 1-9 ◽  
Author(s):  
Wen An Tsou ◽  
Wen Shen Wuen ◽  
Tzu Yi Yang ◽  
Kuei Ann Wen
Keyword(s):  
Output Power ◽  
Power Amplifier ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Source ◽  
Nonlinear Capacitance ◽  
Power Added Efficiency ◽  
Equivalent Impedance ◽  
Common Gate ◽  
Class E

Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

Experimental Study of Class E Family Power Amplifiers with Shunt Filter for Reduced Duty Ratio

2020 ◽  
Author(s):  
Denis Makarov ◽  
Volodymyr Kryzhanovskyi ◽  
Dmytro Chernov ◽  
Vladimir Krizhanovski ◽  
Paolo Colantonio ◽  
...  
Keyword(s):  
Experimental Study ◽  
Power Amplifiers ◽  
Duty Ratio ◽  
Class E
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