Fast Root Cause Analysis Based on Electrical Defect Localization

2008 ◽  
Author(s):  
Michael Schmidt ◽  
Larry Dworkin ◽  
Christopher Hess ◽  
Michele Squcciarini ◽  
Shia Yu ◽  
...  
Keyword(s):  
Root Cause Analysis ◽  
High Density ◽  
Test Structure ◽  
Test Results ◽  
Cause Analysis ◽  
Electrical Test ◽  
Root Cause ◽  
Defect Localization

Abstract The ability to rapidly perform root cause analysis (RCA) on yield limiting defects is critical to a fab’s ramp. Here we present two methodologies for RCA using specially designed high density test structure arrays and a FIB/SEM DualBeam. These methodologies have been proven to identify the root cause of both hard and soft electrical failures. Correlation between electrical test results and the yield-impacting defects are presented.

22 nm BEOL TDDB Defect Localization and Root Cause Analysis

2013 ◽  
Author(s):  
Terence Kane ◽  
Yun Yu Wang
Keyword(s):  
Ion Beam ◽  
Leading Edge ◽  
Root Cause Analysis ◽  
Dielectric Films ◽  
Dielectric Thickness ◽  
Cause Analysis ◽  
Copper Diffusion ◽  
Root Cause ◽  
Defect Localization ◽  
Low K

Abstract For 22nm and below technologies which involve as many as fifteen back end of the line (BEOL) metallization levels, these leading edge technology nodes pose real challenges in defect localization and root cause analysis. Due to scaling, the reduction in copper land cross section area is accompanied by increased current density and electromigration failure rates. Time to Dielectric Defect Breakdown (TDDB) shows an increase in fallout with successive technology node from 32nm and below. Similarly, the reduced dielectric thickness increases the electric field stress prompting the necessity for porous, ultra low k dielectric (ULK) films. Defect localization is difficult due to the complexity of these multiple metal layers along with the presence of the porous, low k dielectric films which exhibit shrinkage or void formation when exposed to an e-beam/FIB ion beam > 1keV. Due to the porosity of these ULK dielectric films, they are especially susceptible to gallium ion implantation. It has been reported elsewhere that suppressing copper diffusion at the copper land/cap interface can be achieved by depositing a thin layer of CoWP and doping the copper seed layer with manganese [15, 16, 17]. However, a method for analytically confirming that these approaches for suppressing the copper diffusion do not affect TDDB performance/electromigration behavior must be demonstrated.

Root Cause analysis of SG tube ODSCC indications within the tube sheets of NPP biblis unit A

2011 ◽  
pp. 78-86
Author(s):  
R. Kilian ◽  
J. Beck ◽  
H. Lang ◽  
V. Schneider ◽  
T. Schönherr ◽  
...  
Keyword(s):  
Root Cause Analysis ◽  
Cause Analysis ◽  
Root Cause

Rule Construction and its Execution for Root Cause Analysis

2012 ◽  
Vol 132 (10) ◽  
pp. 1689-1697
Author(s):  
Yutaka Kudo ◽  
Tomohiro Morimura ◽  
Kiminori Sugauchi ◽  
Tetsuya Masuishi ◽  
Norihisa Komoda
Keyword(s):  
Root Cause Analysis ◽  
Cause Analysis ◽  
Root Cause

Root Cause Analysis Techniques Using Picosecond Time Resolved LADA

2014 ◽  
Author(s):  
Dan Bodoh ◽  
Kent Erington ◽  
Kris Dickson ◽  
George Lange ◽  
Carey Wu ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Picosecond Laser ◽  
Root Cause Analysis ◽  
Fault Isolation ◽  
Time Resolved ◽  
Cause Analysis ◽  
Root Cause ◽  
Design And Manufacturing ◽  
Multiple Interactions ◽  
Established Technique

Abstract Laser-assisted device alteration (LADA) is an established technique used to identify critical speed paths in integrated circuits. LADA can reveal the physical location of a speed path, but not the timing of the speed path. This paper describes the root cause analysis benefits of 1064nm time resolved LADA (TR-LADA) with a picosecond laser. It shows several examples of how picosecond TR-LADA has complemented the existing fault isolation toolset and has allowed for quicker resolution of design and manufacturing issues. The paper explains how TR-LADA increases the LADA localization resolution by eliminating the well interaction, provides the timing of the event detected by LADA, indicates the propagation direction of the critical signals detected by LADA, allows the analyst to infer the logic values of the critical signals, and separates multiple interactions occurring at the same site for better understanding of the critical signals.

Root Cause Analysis for Pin Leakage

2016 ◽  
Author(s):  
Zhigang Song ◽  
Jochonia Nxumalo ◽  
Manuel Villalobos ◽  
Sweta Pendyala
Keyword(s):  
Failure Analysis ◽  
Root Cause Analysis ◽  
Advanced Technology ◽  
Process Step ◽  
Cause Analysis ◽  
Hard Mask ◽  
Technology Node ◽  
Root Cause ◽  
Tools And Techniques

Abstract Pin leakage continues to be on the list of top yield detractors for microelectronics devices. It is simply manifested as elevated current with one pin or several pins during pin continuity test. Although many techniques are capable to globally localize the fault of pin leakage, root cause analysis and identification for it are still very challenging with today’s advanced failure analysis tools and techniques. It is because pin leakage can be caused by any type of defect, at any layer in the device and at any process step. This paper presents a case study to demonstrate how to combine multiple techniques to accurately identify the root cause of a pin leakage issue for a device manufactured using advanced technology node. The root cause was identified as under-etch issue during P+ implantation hard mask opening for ESD protection diode, causing P+ implantation missing, which was responsible for the nearly ohmic type pin leakage.

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