Defect Localization Enhancement Using Light Induced CI-AFP

Author(s):  
N. Dayanand ◽  
A.C.T. Quah ◽  
C.Q. Chen ◽  
S.P. Neo ◽  
G.B. Ang ◽  
...  

Abstract This paper describes the effectiveness of using light induced Current Imaging – Atomic Force Microscopy (CIAFP) to localize defects that are not easily detected through conventional CI-AFP. Defect localization enhancement for both memory and logic failures has been demonstrated. For advanced technology nodes memory failures, current imaging from photovoltaic effects enhanced the detection of bridging between similar types of junctions. Light induced effects also helped to improve the distinction between gated and nongated diode, as a result enhanced localization of gate to source/drain short.

2018 ◽  
Author(s):  
Chuan Zhang ◽  
Jochonia Nxumalo ◽  
Esther P.Y. Chen

Abstract Voltage contrast (VC) mode inline E-beam inspection (EBI) at post contact layer provides electrical readout of critical yield signals at an early stage, which could be months before a wafer reaches functional test. Similar to the passive voltage contrast (PVC) technique that is widely used in failure analysis labs, inline VC scanning is based on scanning electron microscopy, where a low keV electron beam scans across the wafer. Conductive atomic force microscopy (CAFM) was successfully implemented as a characterization method for inline VC defects. In this paper, three challenging VC defect analysis case studies are considered: bright voltage contrast (BVC) gate to active short, BVC Junction leakage, and Dark Voltage Contrast gate contact open. Defects exhibiting a hard electrical short, junctional leakage, and open gate contact are used to illustrate how CAFM provides a powerful and comprehensive solution for in-depth characterization of the inline VC defects.


Author(s):  
Chuan Zhang ◽  
Oh Chong Khiam ◽  
Esther P.Y. Chen

Abstract The increase in complexity of process, structure, and design not only increases the amount of failure analysis (FA) work significantly, but also leads to more complicated failure modes. To meet the need of high success rate and fast throughput FA operation at the leading-edge nodes, novel FA techniques have to be explored and incorporated into the routine FA flow. One of the novel techniques incorporated into the presented scan logic FA flow is the conductive-atomic force microscopy (CAFM) technique. This paper demonstrates CAFM technique as a powerful and efficient solution for scan logic failure analysis at advanced technology nodes. Several failure modes in scan logic FA are used as examples to illustrate how CAFM provides excellent solutions to some of the very challenging FA problems. The gate to active short in nFET devices, resistive contact, and open defect on gate contact are some modes used.


Author(s):  
Chuan Zhang ◽  
Esther P.Y. Chen

Abstract A variety of parametric test structures were designed with the purpose of characterizing parameters tied to failure modes for specific structures, and the electrical test of the parametric test structures are typically conducted earlier inline, which could be months ahead of the functional test. Due to the unique advantages, conductive-atomic force microscopy (CAFM) was introduced to parametric test structure failure analysis during advanced technology development, and has been proven to be a powerful solution to many challenging failure analysis (FA) problems. This paper uses several case studies to illustrate how CAFM can be used to successfully localize defects in challenging parametric test structures that would otherwise be invisible with conventional FA techniques.


Author(s):  
Tom X. Tong ◽  
A. N. Erickson

Abstract Many of the standard techniques of Failure Analysis (FA) are breaking down or becoming less useful as feature sizes drop below 100nm. The tenth micron milestone appears to be a fundamental limitation to many common techniques. Use of Current Image-Atomic Force Microscopy (CI-AFM) combined with Atomic Force Probing (AFP) brings about a combination of technologies, which allow for extension of FA below the nano-scale.


Author(s):  
Z. H. Lee ◽  
C. J. Lin ◽  
S. W. Lai ◽  
J. H. Chou

Abstract This paper describes gate oxide defect localization and analysis using passive voltage contrast (PVC) and conductive atomic force microscopy (C-AFM) in a real product through two case studies. In this paper, 10% wt KOH was used to etch poly-Si and expose gate oxide. In the case studies, different types of gate oxide defects will cause different leakage paths. According to the I-V curve measured by C-AFM, we can distinguish between short mode and gate oxide related leakage. For gate oxide leakage, KOH wet etching was successfully used to identify the gate oxide pinholes.


Author(s):  
Wei-Shan Hu ◽  
Hui-Wen Yang ◽  
Yung-Sheng Huang

Abstract Integrated circuit complexity and density are continuously increasing with the rapid progress of advanced technology nodes. The density of wafer acceptance test (WAT) pattern is also becoming higher as the device continuing to shrink. Failure analysis (FA) techniques have been developed to improve the precision of defect isolation. A technique with more precise fault isolation capability is needed when the test pattern density increased. In this paper we have isolated faults within a dense high Rc array by using conductive atomic force microscopy (C-AFM). The fault sites in the array can be located efficiently with nano-scale precision. Point contact I-V measurements provide a quantitative comparison of the fault sites.


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