scholarly journals Eluding Side Channel Attacks by using Masking 128Bit AES Design

: Advanced encryption standard is detailing for data crypto graphing. The algorithm used universally for cryptography and secure data transmission, the algorithm puissant to intruders, who often attack via side channels. One of the observed attacks was estimate the power implanted in AES core and processed probable scrutinizing to guess the key on multiple iterations. So in order to elude side channel attacks and reduce power consumed in AES standard, design proposed with masking and pipeline scheme. This design helps in shrinking power consumption as compare to AES algorithm and upgrade to withstand from attacks. Another major improvement in the design is LUT’s used for masking and original algorithm almost equal, area phenomenon also solved out. The proposed algorithm implemented in VERTEX-7 FPGA board and simulated using Xilinx Vivado 2015.2 and Modelsim.

2021 ◽  
Author(s):  
R. Sornalatha ◽  
N. Janakiraman ◽  
K. Balamurugan ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  

In this work, we obtain an area proficient composite field arithmetic Advanced Encryption Standard (AES) Substitution (S) byte and its inverse logic design. The size of this design is calculated by the number of gates used for hardware implementation. Most of the existing AES Substitution box hardware implementation uses separate Substitution byte and its inverse hardware structures. But we implement the both in the same module and a control signal is used to select the substitution byte for encryption operation and its inverse for the decryption operation. By comparing the gate utilization of the previous AES S–Box implementation, we reduced the gate utilization up to 5% that is we take only 78 EX-OR gates and 36 AND gates for implementing the both Substitution byte and its inverse. While implementing an AES algorithm in circuitry or programming, it is liable to be detected by hackers using any one of the side channel attacks. Data to be added with a random bit sequence to prevent from the above mentioned side channel attacks.


Author(s):  
Musa. M. Yahaya ◽  
Aminat Ajibola

Recently, the rate of data transfer over the internet globally has increased and this called for more data security as security of data is of great concern for individuals as well as business owners. Cryptography and steganography are two major key players for data security technique. Cryptography is use to perform encryption on the secrete message while steganography hides the secrete message in digital media, image in this regards. This paper employed these two techniques using Advanced Encryption Standard (AES) for the cryptography and Least Significant Bit (LSB) for the steganography. Combining the two algorithms ensured data integrity, data security, and flexibility. The changes in the secrete message carrier (Stego) is insignificant and is often not noticeable by the nicked eyes, thus this make the interception of the message often difficult by intruder.


2019 ◽  
Vol 61 (1) ◽  
pp. 15-28
Author(s):  
Florian Bache ◽  
Christina Plump ◽  
Jonas Wloka ◽  
Tim Güneysu ◽  
Rolf Drechsler

Abstract Side-channel attacks enable powerful adversarial strategies against cryptographic devices and encounter an ever-growing attack surface in today’s world of digitalization and the internet of things. While the employment of provably secure side-channel countermeasures like masking have become increasingly popular in recent years, great care must be taken when implementing these in actual devices. The reasons for this are two-fold: The models on which these countermeasures rely do not fully capture the physical reality and compliance with the requirements of the countermeasures is non-trivial in complex implementations. Therefore, it is imperative to validate the SCA-security of concrete instantiations of cryptographic devices using measurements on the actual device. In this article we propose a side-channel evaluation framework that combines an efficient data acquisition process with state-of-the-art confidence interval based leakage assessment. Our approach allows a sound assessment of the potential susceptibility of cryptographic implementations to side-channel attacks and is robust against noise in the evaluation system. We illustrate the steps in the evaluation process by applying them to a protected implementation of AES.


2021 ◽  
Vol 5 (OOPSLA) ◽  
pp. 1-28
Author(s):  
Robert Brotzman ◽  
Danfeng Zhang ◽  
Mahmut Taylan Kandemir ◽  
Gang Tan

The high-profile Spectre attack and its variants have revealed that speculative execution may leave secret-dependent footprints in the cache, allowing an attacker to learn confidential data. However, existing static side-channel detectors either ignore speculative execution, leading to false negatives, or lack a precise cache model, leading to false positives. In this paper, somewhat surprisingly, we show that it is challenging to develop a speculation-aware static analysis with precise cache models: a combination of existing works does not necessarily catch all cache side channels. Motivated by this observation, we present a new semantic definition of security against cache-based side-channel attacks, called Speculative-Aware noninterference (SANI), which is applicable to a variety of attacks and cache models. We also develop SpecSafe to detect the violations of SANI. Unlike other speculation-aware symbolic executors, SpecSafe employs a novel program transformation so that SANI can be soundly checked by speculation-unaware side-channel detectors. SpecSafe is shown to be both scalable and accurate on a set of moderately sized benchmarks, including commonly used cryptography libraries.


Entropy ◽  
2019 ◽  
Vol 21 (8) ◽  
pp. 781
Author(s):  
Bagus Santoso ◽  
Yasutada Oohama

In this paper, we propose a theoretical framework to analyze the secure communication problem for broadcasting two encrypted sources in the presence of an adversary which launches side-channel attacks. The adversary is not only allowed to eavesdrop the ciphertexts in the public communication channel, but is also allowed to gather additional information on the secret keys via the side-channels, physical phenomenon leaked by the encryption devices during the encryption process, such as the fluctuations of power consumption, heat, or electromagnetic radiation generated by the encryption devices. Based on our framework, we propose a countermeasure against such adversary by using the post-encryption-compression (PEC) paradigm, in the case of one-time-pad encryption. We implement the PEC paradigm using affine encoders constructed from linear encoders and derive the explicit the sufficient conditions to attain the exponential decay of the information leakage as the block lengths of encrypted sources become large. One interesting feature of the proposed countermeasure is that its performance is independent from the type of side information leaked by the encryption devices.


Data transmission with protection is main concept which is getting demand now a days for which number of encryption of data techniques are developed and now in this paper Advanced Encryption Standard (AES) Algorithm is used and is implemented on FPGA kit using vertex-3 family. We use 128 bits consists of input, key data, output data for this design. It is called an iterative looping with replacement box, key, loop in this design for both encryption and decryption of data. We use Xilinx software platform for simulation of our design that is AES by which area utilization and throughput is increased for achieving low power consumption, high data security, reduced latency and easy architectural design. This data operation is applicable in many areas.


Author(s):  
Meenakshi R. K ◽  
A. Arivazhagan

<p>The demand of satellite communication, the security algorithms are to be designed in the board. The information from the satellite to the ground is required the data security with the cryptographic algorithms. Advanced encryption standard (AES) is one of the promising cryptographic algorithms for the terrestrial communication. In this paper, the encryption and decryption is mainly focused on the cipher block chaining (CBC) mode for achieving the high secured data transmission. For efficient data transmission, the AES algorithm is implemented by using CBC mode. The proposed work is designed by using RTL modeling and also the minimum numbers of logical elements are used for implementation. </p>


Author(s):  
Ishpal Singh Gill ◽  
Dharm Singh Jat

Internet of things (IoT) is a rapidly emerging architecture connecting smart devices all across the world in various fields like smart homes, smart cities, health sector, security, etc. Security is a very important aspect of IoT. As more and more devices are connecting to the Internet, it becomes a lucrative target for hackers. The communication between the various devices, nodes, and between nodes and the cloud, needs to be secured. A combination of public and private key cryptography systems is used to secure the IoT networks. The Advanced Encryption Standard (AES) is used for encrypting the data in transit. However, the AES is known to be prone to brute force attacks, side channel attacks, and other forms of cryptanalysis. This chapter proposes a more secure AES algorithm with randomised round keys, which provides better security with negligible overheads, and is ideal for use in IoT networks.


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