Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

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Conduction Uniformity Improvement of ESD Protection Device in 0.35 μm Partially-Depleted SOI Salicided CMOS Technology

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.687-691.3251 ◽

2014 ◽

Vol 687-691 ◽

pp. 3251-3254

Author(s):

Zhuo Tian ◽

Bai Cheng Li

Keyword(s):

Cmos Technology ◽

Alpha Particles ◽

Soft Error ◽

Silicon On Insulator ◽

Low Power Consumption ◽

Protection Device ◽

Low Leakage ◽

Low Leakage Current ◽

Esd Protection ◽

Soi Technology

ComparedtobulkCMOStechnology,Silicon-on-Insulator (SOI) CMOS technology has many advantages, such as low power consumption, low leakage current, low parasitic capacitance and a low soft error rate from both alpha particles and cosmic rays. However,electrostatic discharge (ESD) protection in SOI technology is still a major substantial barrier to overcome for the poor thermal conductivity of isolation oxide and the absence of vertical diode and silicon controlled rectifier (SCR).

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Integration of STT-MRAMs for Embedded Cache Memories

Advances in Science and Technology ◽

10.4028/www.scientific.net/ast.95.146 ◽

2014 ◽

Vol 95 ◽

pp. 146-149

Author(s):

Toshihiro Sugii ◽

Yoshihisa Iba ◽

Masaki Aoki ◽

Hideyuki Noshiro ◽

Kouji Tsunoda ◽

...

Keyword(s):

Dielectric Breakdown ◽

Magnetic Tunnel Junction ◽

Spin Transfer Torque ◽

Spin Transfer ◽

Cache Memory ◽

Current Status ◽

Cache Memories ◽

Time Dependent Dielectric Breakdown ◽

Memory Applications ◽

Embedded Sram

We report the current status of our development of spin-transfer torque magnetic RAMs (STT-MRAMs) and their integration with the back-end-of-line (BEOL) process to replace conventional embedded SRAM cache memories. Our MRAM technology features a top-pinned, perpendicular magnetic tunnel junction (MTJ) and a highly reliable MTJ for a cache memory. We could obtain a higher density cache memory than that with conventional SRAMs with our STT-MRAMs, and leakage free characteristics, as well as unlimited write and read cycling times and 10-year time-dependent dielectric breakdown (TDDB) characteristics. They were integrated into Cu interconnects with 300 mm facilities. We also discuss variations in MTJ pattern sizes that are very important for memory applications from the viewpoint of high density embedded cache memories.

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Low-leakage soft error tolerant port-less configuration memory cells for FPGAs

Integration ◽

10.1016/j.vlsi.2012.08.001 ◽

2013 ◽

Vol 46 (4) ◽

pp. 413-426 ◽

Cited By ~ 1

Author(s):

Arash Azizi Mazreah ◽

Mohammad T. Manzuri Shalmani

Keyword(s):

Soft Error ◽

Memory Cells ◽

Low Leakage

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A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies

Advances in Radio Science ◽

10.5194/ars-3-355-2005 ◽

2005 ◽

Vol 3 ◽

pp. 355-358

Author(s):

A. Schmitz ◽

R. Tielert

Keyword(s):

Supply Voltage ◽

Logic Gate ◽

Deep Submicron ◽

Soft Error ◽

Sleep Mode ◽

Leakage Currents ◽

Low Leakage ◽

Sram Cell ◽

Local Supply ◽

Standby Mode

Abstract. Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate. To maintain the high switching performance, the threshold voltage must be scaled according with the supply voltage. However, this leads to an increased subthreshold current of the transistors in standby mode (VGS=0). Another source of leakage is gate current, which becomes significant for gate oxides of 3nm and below. We propose a Self-Biasing Virtual Rails (SBVR) - CMOS technique which acts like an adaptive local supply voltage in case of standby mode. Most important sources of leakage currents are reduced by this technique. Moreover, SBVR-CMOS is capable of conserving stored information in sleep mode, which is vital for memory circuits. Memories are exposed to radiation causing soft errors. This well-known problem becomes even worse in standby mode of typical SRAMs, that have low driving performance to withstand alpha particle hits. In this paper, a 16-transistor SRAM cell is proposed, which combines the advantage of extremely low leakage currents with a very high soft error stability.

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High Read Stability and Low Leakage Cache Memory Cell

2007 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2007.378628 ◽

2007 ◽

Cited By ~ 30

Author(s):

Zhiyu Liu ◽

Volkan Kursun

Keyword(s):

Memory Cell ◽

Cache Memory ◽

Low Leakage

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Properties of Thin Inter-Polysilicon Reoxidized Nitrided Oxides Prepared by Rapid Thermal Processing (RTO/RTN/RTO)

MRS Proceedings ◽

10.1557/proc-146-483 ◽

1989 ◽

Vol 146 ◽

Cited By ~ 1

Author(s):

Andrew W. Cheung ◽

G. Q. Lo ◽

Dim-Lee Kwong ◽

N. S. Alvi ◽

A. Kermani

Keyword(s):

Thermal Processing ◽

Rapid Thermal Processing ◽

Dielectric Strength ◽

Breakdown Field ◽

Low Leakage ◽

Low Leakage Current ◽

Thermal Oxide ◽

Non Volatile Memory ◽

Thermal Nitridation ◽

Memory Applications

ABSTRACTIn the search of a high quality thin inter-polysilicon dielectric which has high breakdown voltage and low leakage current for high density non-volatile memory applications, thin (150±) inter-polysilicon reoxidized nitrided oxide capacitors were fabricated with multiple rapid thermal processing. While rapid thermal nitridation degraded the breakdown field if compared to the rapid thermal oxide capacitors, rapid thermal reoxidation greatly enhanced the dielectric strength of the rapid thermal nitrided samples. The short reoxidations increased the film thickness by less than 10 \. Breakdown field of optimized inter-polysilicon RTO/RTN/RTO capacitors up to 14 MV/cm has been measured.

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