A Parallel Perifusion Slide From Glass for the Functional and Morphological Analysis of Pancreatic Islets

An islet-on-chip system in the form of a completely transparent microscope slide optically accessible from both sides was developed. It is made from laser-structured borosilicate glass and enables the parallel perifusion of five microchannels, each containing one islet precisely immobilized in a pyramidal well. The islets can be in inserted via separate loading windows above each pyramidal well. This design enables a gentle, fast and targeted insertion of the islets and a reliable retention in the well while at the same time permitting a sufficiently fast exchange of the media. In addition to the measurement of the hormone content in the fractionated efflux, parallel live cell imaging of the islet is possible. By programmable movement of the microscopic stage imaging of five wells can be performed. The current chip design ensures sufficient time resolution to characterize typical parameters of stimulus-secretion coupling. This was demonstrated by measuring the reaction of the islets to stimulation by glucose and potassium depolarization. After the perifusion experiment islets can be removed for further analysis. The live-dead assay of the removed islets confirmed that the process of insertion and removal was not detrimental to islet structure and viability. In conclusion, the present islet-on-chip design permits the practical implementation of parallel perifusion experiments on a single and easy to load glass slide. For each immobilized islet the correlation between secretion, signal transduction and morphology is possible. The slide concept allows the scale-up to even higher degrees of parallelization.

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Analysis of the Practical Implementation of Flicker Measurement Coprocessor for AMI Meters

Energies ◽

10.3390/en14061589 ◽

2021 ◽

Vol 14 (6) ◽

pp. 1589

Author(s):

Krzysztof Kołek ◽

Andrzej Firlit ◽

Krzysztof Piątek ◽

Krzysztof Chmielowiec

Keyword(s):

Code Generation ◽

State Of The Art ◽

Power Grids ◽

Practical Implementation ◽

System A ◽

Measuring Devices ◽

Point Representation ◽

Measurement Algorithm ◽

On Chip ◽

Vhdl Code

Monitoring power quality (PQ) indicators is an important part of modern power grids’ maintenance. Among different PQ indicators, flicker severity coefficients Pst and Plt are measures of voltage fluctuations. In state-of-the-art PQ measuring devices, the flicker measurement channel is usually implemented as a dedicated processor subsystem. Implementation of the IEC 61000-4-15 compliant flicker measurement algorithm requires a significant amount of computational power. In typical PQ analysers, the flicker measurement is usually implemented as a part of the meter’s algorithm performed by the main processor. This paper considers the implementation of the flicker measurement as an FPGA module to offload the processor subsystem or operate as an IP core in FPGA-based system-on-chip units. The measurement algorithm is developed and validated as a Simulink diagram, which is then converted to a fixed-point representation. Parts of the diagram are applied for automatic VHDL code generation, and the classifier block is implemented as a local soft-processor system. A simple eight-bit processor operates within the flicker measurement coprocessor and performs statistical operations. Finally, an IP module is created that can be considered as a flicker coprocessor module. When using the coprocessor, the main processor’s only role is to trigger the coprocessor and read the results, while the coprocessor independently calculates the flicker coefficients.

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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

On Chip

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Building a multi-FPGA-based emulation framework to support networks-on-chip design and verification

International Journal of Electronics ◽

10.1080/00207217.2010.512017 ◽

2010 ◽

Vol 97 (10) ◽

pp. 1241-1262 ◽

Cited By ~ 9

Author(s):

Yangfan Liu ◽

Peng Liu ◽

Yingtao Jiang ◽

Mei Yang ◽

Kejun Wu ◽

...

Keyword(s):

Support Networks ◽

Chip Design ◽

Networks On Chip ◽

On Chip

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Integration of Al-Fill Processes for Contacts and VIAS

MRS Proceedings ◽

10.1557/proc-427-253 ◽

1996 ◽

Vol 427 ◽

Cited By ~ 9

Author(s):

H. J. Barth

Keyword(s):

High Pressure ◽

Chip Design ◽

Size And Shape ◽

Future Developments ◽

Pattern Density ◽

New Challenges ◽

On Chip ◽

Damascene Interconnects ◽

Low K ◽

Electrical Data

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.

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