scholarly journals Extending NUMA-BTLP Algorithm with Thread Mapping Based on a Communication Tree

Computers ◽  
2018 ◽  
Vol 7 (4) ◽  
pp. 66
Author(s):  
Iulia Știrb

The paper presents a Non-Uniform Memory Access (NUMA)-aware compiler optimization for task-level parallel code. The optimization is based on Non-Uniform Memory Access—Balanced Task and Loop Parallelism (NUMA-BTLP) algorithm Ştirb, 2018. The algorithm gets the type of each thread in the source code based on a static analysis of the code. After assigning a type to each thread, NUMA-BTLP Ştirb, 2018 calls NUMA-BTDM mapping algorithm Ştirb, 2016 which uses PThreads routine pthread_setaffinity_np to set the CPU affinities of the threads (i.e., thread-to-core associations) based on their type. The algorithms perform an improve thread mapping for NUMA systems by mapping threads that share data on the same core(s), allowing fast access to L1 cache data. The paper proves that PThreads based task-level parallel code which is optimized by NUMA-BTLP Ştirb, 2018 and NUMA-BTDM Ştirb, 2016 at compile-time, is running time and energy efficiently on NUMA systems. The results show that the energy is optimized with up to 5% at the same execution time for one of the tested real benchmarks and up to 15% for another benchmark running in infinite loop. The algorithms can be used on real-time control systems such as client/server based applications which require efficient access to shared resources. Most often, task parallelism is used in the implementation of the server and loop parallelism is used for the client.


Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 211 ◽  
Author(s):  
Ionel Zagan ◽  
Vasile Găitan

The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response speed and performance of real-time systems. Software implementations of RTOS-specific functions can generate significant delays, adversely affecting the deadlines required for certain applications. This paper presents an original implementation of a dedicated processor, based on multiple pipeline registers, and a hardware support for a dynamic scheduler with the following characteristics: performs unitary event management, provides access to architecture shared resources, prioritizes and executes the multiple events expected by the same task. The paper also presents a method through which interrupts are assigned to tasks. Through dedicated instructions, the integrated hardware scheduler implements tasks synchronization with multiple prioritized events, thus ensuring an efficient functioning of the processor in the context of real-time control.



1995 ◽  
Vol 34 (05) ◽  
pp. 475-488
Author(s):  
B. Seroussi ◽  
J. F. Boisvieux ◽  
V. Morice

Abstract:The monitoring and treatment of patients in a care unit is a complex task in which even the most experienced clinicians can make errors. A hemato-oncology department in which patients undergo chemotherapy asked for a computerized system able to provide intelligent and continuous support in this task. One issue in building such a system is the definition of a control architecture able to manage, in real time, a treatment plan containing prescriptions and protocols in which temporal constraints are expressed in various ways, that is, which supervises the treatment, including controlling the timely execution of prescriptions and suggesting modifications to the plan according to the patient’s evolving condition. The system to solve these issues, called SEPIA, has to manage the dynamic, processes involved in patient care. Its role is to generate, in real time, commands for the patient’s care (execution of tests, administration of drugs) from a plan, and to monitor the patient’s state so that it may propose actions updating the plan. The necessity of an explicit time representation is shown. We propose using a linear time structure towards the past, with precise and absolute dates, open towards the future, and with imprecise and relative dates. Temporal relative scales are introduced to facilitate knowledge representation and access.





2007 ◽  
Vol 73 (12) ◽  
pp. 1369-1374
Author(s):  
Hiromi SATO ◽  
Yuichiro MORIKUNI ◽  
Kiyotaka KATO


2020 ◽  
Vol 21 (3) ◽  
pp. 296-302
Author(s):  
A. V. Aab ◽  
◽  
P. V. Galushin ◽  
A. V. Popova ◽  
V. A. Terskov ◽  
...  


Author(s):  
Vladimir V. NEKRASOV

Developing a microcontroller-based system for controlling the flywheel motor of high-dynamics spacecraft using Russian-made parts and components made it possible to make statement of the problem of searching control function for a preset rotation rate of the flywheel rotor. This paper discusses one of the possible options for mathematical study of the stated problem, namely, application of structural analysis based on graph theory. Within the framework of the stated problem a graph was constructed for generating the new required rate, while in order to consider the stochastic case option the incidence and adjacency matrices were constructed. The stated problem was solved using a power matrix which transforms a set of contiguous matrices of the graph of admissible solution edge sequences, the real-time control function was found. Based on the results of this work, operational trials were run for the developed control function of the flywheel motor rotor rotation rate, a math model was constructed for the real-time control function, and conclusions were drawn about the feasibility of implementing the results of this study. Key words: Control function, graph, incidence matrix, adjacency matrix, power matrix, microcontroller control of the flywheel motor, highly dynamic spacecraft.



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