scholarly journals Experimental Efficiency Evaluation of Stacked Transistor Half-Bridge Topologies in 14 nm CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (10) ◽  
pp. 1150
Author(s):  
Pedro André Martins Martins Bezerra ◽  
Florian Krismer ◽  
Johann Walter Kolar ◽  
Riduan Khaddam-Aljameh ◽  
Stephan Paredes ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Output Current ◽  
Maximum Current ◽  
High Maximum ◽  
Power Switches ◽  
Converter Topologies ◽  
Microprocessor Application ◽  
High Output

Different Half-Bridge (HB) converter topologies for an Integrated Voltage Regulator (IVR), which serves as a microprocessor application, were evaluated. The HB circuits were implemented with Stacked Transistors (HBSTs) in a cutting-edge 14 nm CMOS technology node in order to enable the integration on the microprocessor die. Compared to a conventional realization of the HBST, it was found that the Active Neutral-Point Clamped (ANPC) HBST topology with Independent Clamp Switches (ICSs) not only ensured balanced blocking voltages across the series-connected transistors, but also featured a more robust operation and achieved higher efficiencies at high output currents. The IVR achieved a maximum efficiency of 85.3% at an output current of 300 mA and a switching frequency of 50 MHz. At the maximum measured output current of 780 mA, the efficiency was 83.1%. The active part of the IVR (power switches, gate-drivers, and level shifters) realized a high maximum current density of 24.7 A/mm2.

scholarly journals Asymmetrical ZVS-PWM Switched-Capacitor Based Half-Bridge DC-DC Converter With Switch Peak Voltage of Vin/2

2020 ◽  
Author(s):  
Angelica Paula Caus ◽  
Guilherme Martins Leandro ◽  
Ivo Barbi
Keyword(s):  
Theoretical Analysis ◽  
Power Converter ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Switched Capacitor ◽  
Peak Voltage ◽  
Zero Voltage Switching ◽  
Power Switches ◽  
Converter Topology ◽  
Bus Voltage

This paper presents a new power converter topology<br>generated by the integration of the asymmetrical ZVS-PWM dcdc converter with a switched-capacitor ladder-type commutation<br>cell. Circuit operation and theoretical analysis with emphasis on<br>the soft-commutation process are included in the paper. The<br>main advantage of the proposed converter with respect to the<br>conventional asymmetrical half-bridge dc-dc converter is the<br>reduction of the voltage stress across the power switches to the<br>half of the input dc bus voltage, enabling the utilization of lower<br>voltage rating components. Experiments conducted on a<br>laboratory prototype with 1.4 kW power-rating, 800 V input<br>voltage, 48 V output voltage and 100 kHz switching frequency<br>are included, to verify the theoretical analysis and the design<br>methodology. The maximum efficiency of the experimental nonoptimized prototype was 93.6%.<br>Index Terms - Asymmetrical dc-dc converter, pulse-widthmodulation, switched-capacitor, zero voltage switching.<div><br><br></div>

scholarly journals Asymmetrical ZVS-PWM Switched-Capacitor Based Half-Bridge DC-DC Converter With Switch Peak Voltage of Vin/2

2020 ◽  
Author(s):  
Angelica Paula Caus
Keyword(s):  
Theoretical Analysis ◽  
Power Converter ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Switched Capacitor ◽  
Peak Voltage ◽  
Zero Voltage Switching ◽  
Power Switches ◽  
Converter Topology ◽  
Bus Voltage

This paper presents a new power converter topology<br>generated by the integration of the asymmetrical ZVS-PWM dcdc converter with a switched-capacitor ladder-type commutation<br>cell. Circuit operation and theoretical analysis with emphasis on<br>the soft-commutation process are included in the paper. The<br>main advantage of the proposed converter with respect to the<br>conventional asymmetrical half-bridge dc-dc converter is the<br>reduction of the voltage stress across the power switches to the<br>half of the input dc bus voltage, enabling the utilization of lower<br>voltage rating components. Experiments conducted on a<br>laboratory prototype with 1.4 kW power-rating, 800 V input<br>voltage, 48 V output voltage and 100 kHz switching frequency<br>are included, to verify the theoretical analysis and the design<br>methodology. The maximum efficiency of the experimental nonoptimized prototype was 93.6%.<br>Index Terms - Asymmetrical dc-dc converter, pulse-widthmodulation, switched-capacitor, zero voltage switching.<div><br><br></div>

Non-Isolated High Step Up in Voltage DC–DC Converter Topology for Renewable Applications

2020 ◽  
pp. 2150093
Author(s):  
Pavan Prakash Gupta ◽  
G. Indira Kishore ◽  
Ramesh Kumar Tripathi
Keyword(s):  
High Voltage ◽  
Switching Frequency ◽  
Resistive Load ◽  
Voltage Gain ◽  
Boost Converters ◽  
High Voltage Gain ◽  
Voltage Stress ◽  
Power Switches ◽  
Converter Topologies ◽  
Converter Topology

In the class of the boost converters, the conventional DC–DC boost converters are in common practice but their limited boost capabilities at higher duty ratios are one of the concerns. The isolated and non-isolated step-up DC–DC converters are one of the remedies of the above issue. The presence of switched inductor and switched capacitors in the circuit of non-isolated configuration can provide considerable step-up in voltage at the output, and also facilitate lower voltage stress on components. In this paper, work has been done to propose three non-isolated high-voltage gain DC–DC boost converter topologies. Along with the high voltage gain, the topologies also have lesser voltage stress across the active power switches and diodes used in topologies. The proposed topologies are suitable for low dc input levels like renewable sources, microgrid and grid-connected applications. A Matlab/Simulink 2017a environment is utilized to derive, design and simulate the proposed topologies for a 100-W load operation. The basic topology is also realized in hardware as a prototype circuit with 100-W resistive load, operated at 50[Formula: see text]kHz switching frequency.

scholarly journals Asymmetrical ZVS-PWM Switched-Capacitor Based Half-Bridge DC-DC Converter With Switch Peak Voltage of Vin/2

2020 ◽  
Author(s):  
Angelica Paula Caus ◽  
Guilherme Martins Leandro ◽  
Ivo Barbi
Keyword(s):  
Theoretical Analysis ◽  
Power Converter ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Switched Capacitor ◽  
Peak Voltage ◽  
Zero Voltage Switching ◽  
Power Switches ◽  
Converter Topology ◽  
Bus Voltage

This paper presents a new power converter topology<br>generated by the integration of the asymmetrical ZVS-PWM dcdc converter with a switched-capacitor ladder-type commutation<br>cell. Circuit operation and theoretical analysis with emphasis on<br>the soft-commutation process are included in the paper. The<br>main advantage of the proposed converter with respect to the<br>conventional asymmetrical half-bridge dc-dc converter is the<br>reduction of the voltage stress across the power switches to the<br>half of the input dc bus voltage, enabling the utilization of lower<br>voltage rating components. Experiments conducted on a<br>laboratory prototype with 1.4 kW power-rating, 800 V input<br>voltage, 48 V output voltage and 100 kHz switching frequency<br>are included, to verify the theoretical analysis and the design<br>methodology. The maximum efficiency of the experimental nonoptimized prototype was 93.6%.<br>Index Terms - Asymmetrical dc-dc converter, pulse-widthmodulation, switched-capacitor, zero voltage switching.<div><br><br></div>

scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

Design of a High-Precision Flyback Constant Voltage AC–DC Converter

2017 ◽  
Vol 26 (11) ◽  
pp. 1750175
Author(s):  
Changyuan Chang ◽  
Chao Hong ◽  
Yang Xu ◽  
Hailong Sun ◽  
Yao Chen
Keyword(s):  
High Precision ◽  
Output Voltage ◽  
Control Method ◽  
Switching Frequency ◽  
Constant Voltage ◽  
Light Load ◽  
Wave Generator ◽  
Load Regulation ◽  
High Output

A constant voltage AC–DC converter based on the digital assistant technology is proposed in this paper, which has the advantage of high output precision. In this paper, a novel digital exponential wave generator is adopted in Constant Voltage (CV) mode to replace the normal triangle waveform to obtain a wider range of switching frequency, increasing the accuracy of output voltage under light load. The control chip is implemented based on NEC 1[Formula: see text][Formula: see text]m 5[Formula: see text]V/40[Formula: see text]V HVCMOS process, and a 5[Formula: see text]V/1.2[Formula: see text]A prototype has been built to verify the proposed control method. In PFM mode the deviation of output voltage is within [Formula: see text]% and the load regulation is [Formula: see text]%. Meanwhile, when the load jumps from light to heavy, the minimum output voltage could be maintained above 4.16[Formula: see text]V.

Sign in / Sign up

Export Citation Format

Share Document