scholarly journals Design of an Ultra-Low Voltage Bias Current Generator Highly Immune to Electromagnetic Interference

2021 ◽  
Vol 11 (1) ◽  
pp. 6
Author(s):  
Orazio Aiello
Keyword(s):  
Integrated Circuits ◽  
Electromagnetic Interference ◽  
Low Voltage ◽  
Current Source ◽  
Building Blocks ◽  
Cmos Technology ◽  
Threshold Region ◽  
Output Current ◽  
Current Generator ◽  
Technology Process

The paper deals with the immunity to Electromagnetic Interference (EMI) of the current source for Ultra-Low-Voltage Integrated Circuits (ICs). Based on the properties of IC building blocks, such as the current-splitter and current correlator, a novel current generator is conceived. The proposed solution is suitable to provide currents to ICs operating in the sub-threshold region even in the presence of an electromagnetic polluted environment. The immunity to EMI of the proposed solution is compared with that of a conventional current mirror and evaluated by analytic means and with reference to the 180 nm CMOS technology process. The analysis highlights how the proposed solution generates currents down to nano-ampere intrinsically robust to the Radio Frequency (RF) interference affecting the input of the current generator, differently to what happens to the output current of a conventional mirror under the same conditions.

Nano Power Current Reference Circuit consisting of Sub-threshold CMOS Circuits

2017 ◽  
Vol 2 (1) ◽  
pp. 1-4
Author(s):  
Dinesh Kushwaha ◽  
D. K. Mishra
Keyword(s):  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Cmos Technology ◽  
Threshold Region ◽  
Voltage Range ◽  
Current Reference ◽  
Reference Circuit

This paper proposes a low voltage CMOS Nano power current reference circuit and presents its performance with circuit simulation in 180- nm UMC CMOS technology. The proposed circuit consists of start-up, Bias-voltage, current-source sub-circuits with most of the MOSFETs operating in sub-threshold region. Simulation results shows that the circuit generates a stable reference current of 4-nA in supply voltage range 1 V- 1.8 V with line sensitivity of 0.203%/V.The temperature coefficient of the current was 7592ppm/°C at 1.8 V in the range of 0°C-100°C. The power dissipation was 380 NW at 1.8 V Supply. The proposed circuit would be suitable for use in sub-threshold –operated power-aware large-scale integration

scholarly journals A reference current source with a low temperature coefficient

2018 ◽  
Vol 232 ◽  
pp. 04077
Author(s):  
DongYang Han ◽  
XiaoNing Xin ◽  
GuoFeng Liu
Keyword(s):  
Low Temperature ◽  
Integrated Circuits ◽  
Temperature Coefficient ◽  
Current Source ◽  
Output Current ◽  
High Demand ◽  
Temperature Characteristics ◽  
Advantages And Disadvantages ◽  
Circuit Structure ◽  
Typical Process

In view of the high demand for low temperature coefficient reference current sources in integrated circuits, the advantages and disadvantages of several typical reference current sources in circuit structure and temperature characteristics are compared. In this paper, a low temperature coefficient reference current source is designed. Based on Hua Hong HHNECGE 0.35um process, the output current is 0.4uA, the temperature range is -40°C-125°C, and the temperature coefficient is 7.6ppm/°C under typical process angle. Other processes The temperature coefficient under the corner is at 10ppm/°C.

scholarly journals A New Low-Voltage Low-Power Dual-Mode VCII-Based SIMO Universal Filter

Electronics ◽  
2019 ◽  
Vol 8 (7) ◽  
pp. 765 ◽  
Author(s):  
Leila Safari ◽  
Gianluca Barile ◽  
Giuseppe Ferri ◽  
Vincenzo Stornelli
Keyword(s):  
Low Power ◽  
Transfer Functions ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Technology ◽  
Universal Filter ◽  
Dual Mode ◽  
Input Multiple Output ◽  
Low Pass

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 μm CMOS technology parameters at a supply voltage of ±0.9 V are provided to support the presented theory.

scholarly journals Design techniques for low-voltage analog integrated circuits

2017 ◽  
Vol 68 (4) ◽  
pp. 245-255 ◽  
Author(s):  
Matej Rakús ◽  
Viera Stopjaková ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Low Voltage ◽  
Supply Voltage ◽  
Building Blocks ◽  
Cmos Process ◽  
Mos Transistors ◽  
Power Supply Voltage ◽  
Current Mirrors ◽  
Moderate Inversion ◽  
Design Techniques

AbstractIn this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

scholarly journals Nano Power Current Reference Circuit Consisting of Sub-threshold CMOS Circuits

2019 ◽  
Vol 9 (1) ◽  
pp. 4657-4660
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Simulation ◽  
Current Source ◽  
Threshold Power ◽  
Threshold Region ◽  
Voltage Range ◽  
Simulation Performance ◽  
Current Reference ◽  
Reference Circuit

a low voltage CMOS Nano power current reference circuit has been presented in this paper and also the circuit simulation performance in 180-nm UMC CMOS technology. Most of the MOSFETs operate in sub-threshold region consisting of bias-voltage, start-up and current-source sub-circuits. A stable reference current of 4-nA lying in supply voltage range of 1 V-1.8 V has been generated with line sensitivity of 0.203% /V. Within the temperature range of 0°C to 100 °C, and the voltage level of 1.8 V, the temperature coefficient was 7592ppm/°C. At the same voltage supply, the power dissipation was found out to be 380 NW. It is suitable to use this circuit in sub threshold power aware large scale integration.

An Ultra-Low-Voltage Low-Power Current-Mode True RMS-to-DC Converter

2016 ◽  
Vol 25 (06) ◽  
pp. 1650066 ◽  
Author(s):  
Pantre Kompitaya ◽  
Khanittha Kaewdang
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Performance ◽  
Dynamic Range ◽  
Low Voltage ◽  
Supply Voltage ◽  
Circuit Complexity ◽  
Current Mode ◽  
Cmos Technology ◽  
Low Supply Voltage

A current-mode CMOS true RMS-to-DC (RMS: root-mean-square) converter with very low voltage and low power is proposed in this paper. The design techniques are based on the implicit computation and translinear principle by using CMOS transistors that operate in the weak inversion region. The circuit can operate for two-quadrant input current with wide input dynamic range (0.4–500[Formula: see text]nA) with an error of less than 1%. Furthermore, its features are very low supply voltage (0.8[Formula: see text]V), very low power consumption ([Formula: see text]0.2[Formula: see text]nW) and low circuit complexity that is suitable for integrated circuits (ICs). The proposed circuit is designed using standard 0.18[Formula: see text][Formula: see text]m CMOS technology and the HSPICE simulation results show the high performance of the circuit and confirm the validity of the proposed design technique.

scholarly journals IDDQ Testing of Low Voltage CMOS Operational Transconductance Amplifier

2018 ◽  
Vol 8 (3) ◽  
pp. 1467 ◽  
Author(s):  
Maninder Kaur ◽  
Jasdeep Kaur
Keyword(s):  
Power Supply ◽  
Low Voltage ◽  
Fault Injection ◽  
Current Source ◽  
Cmos Technology ◽  
Injection Technique ◽  
Voltage Reference ◽  
Iddq Testing ◽  
Supply Current ◽  
Circuit Under Test

The paper describes the design for testability (DFT) of low voltage two stage operational transconductance amplifiers based on quiescent power supply current (IDDQ) testing. IDDQ testing refers to the integral circuit testing method based upon measurement of steady state power supply current for testing both digital as well as analog VLSI circuit. A built in current sensor, which introduces insignificant performance degradation of the circuit-under-test, has been proposed to monitor the power supply quiescent current changes in the circuit under test. Moreover, the BICS requires neither an external voltage reference nor a current source and able to detect, identify and localize the circuit faults. Hence the BICS requires less area and is more efficient than the conventional current sensors. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. Both bridging and open faults have been analyzed in proposed work by using n-well 0.18µm CMOS technology.

Optimization of building blocks for multi-stage 17–44 dB 6.1–9.6 mW 90-nm K-band front-ends

2013 ◽  
Vol 3 (4) ◽  
Author(s):  
Apratim Roy ◽  
A. Harun Rashid
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Optimization Procedure ◽  
Building Blocks ◽  
Cmos Technology ◽  
Power Requirement ◽  
Reverse Isolation ◽  
Multi Stage ◽  
Forward Gain ◽  
K Band

AbstractIn this article, five two-stage ∼6-mW and four three-stage ∼9-mW matched amplifier architectures are proposed to establish optimization procedure and quantify relative merits of cascode (CC), common-gate (CG), and commonsource (CS) building blocks for low-voltage low-power multi-stage front-ends. The circuits are simulated with a 90-nm CMOS technology including modeling of layout parasites. Integrated bias trees and passive port matching networks are incorporated in the K-band designs. In the face of process mismatch, variability in noise and gain figures remains <0.39 dB and <7.1 dB from the design values. The five combinations of building blocks in twostage low-power (6.1–6.6 mW) amplifiers achieve linearity (IIP3) in the range of −5.2∼–13.5 dBm, good reverse isolation (better than −26 dB), 2.89–3.82 dB noise penalties, and 17.2–25.5 dB peak forward gain. In case of threestage front-ends built with CS, CC, and CG blocks (power rating 9.2–9.6 mW), forward gain and optimized noise figures are found as >33 dB and <3.26 dB, respectively. They achieve −2.5∼18.3 dBm IIP3, <−39 dB reverse isolation, and <−17 dB minimum IRL. The results are compared with reported simulated findings on CMOS multistage amplifiers to highlight their relative advantages in terms of power requirement and decibel(gain)-per-watt.

scholarly journals Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods

2014 ◽  
Vol 2014 ◽  
pp. 1-8 ◽  
Author(s):  
Maneesha Gupta ◽  
Urvashi Singh ◽  
Richa Srivastava
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Current Mirror ◽  
Bandwidth Extension ◽  
High Compliance ◽  
Compensation Methods ◽  
Inductive Peaking ◽  
Cascode Current Mirror

Due to the huge demand of high-speed analog integrated circuits, it is essential to develop a wideband low input impedance current mirror that can be operated at low power supply. In this paper, a novel wideband low voltage high compliance current mirror using low voltage cascode current mirror (LVCCM) as a basic building block is proposed. The resistive compensation and inductive peaking methods have been used to extend the bandwidth of the conventional current mirror. By replacing conventional LVCCM in a high compliance current mirror with the compensated LVCCM, the bandwidth extension ratio of 3.4 has been achieved with no additional DC power dissipation and without affecting its other performances. The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.

Analysis the Interface of Amplifier in GPON System by PSpice

2010 ◽  
Vol 44-47 ◽  
pp. 3833-3838
Author(s):  
Li Li ◽  
Ji Jun Zhang
Keyword(s):  
Integrated Circuits ◽  
Interface Design ◽  
Low Voltage ◽  
Model Simulation ◽  
Impedance Matching ◽  
Current Source ◽  
Current Mode ◽  
Matching Problem ◽  
Differential Signal ◽  
Macro Model

Model help to understand the system there may be a signal reflection and impedance matching problem. Most fiber integrated circuits from Maxim use Current Mode Logic (CML), Positive Emitter Coupled Logic (PECL), and Low Voltage Differential Signal (LVDS) I/O formats. Language can be set up through the PSpice circuit model of the IC, with an ideal voltage controlled current source of alternative sources and active circuit elements. And the use of spice macro-model simulation to test the circuit performance of the chip interface design. In this paper, it takes the model of amplifier IC in GPON receiver front-end for example to shows the steps and importance of interface simulation in GPON system by PSpice macro-model.

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