scholarly journals Gate All around with Back Gate NAND Flash Structure for Excellent Reliability Characteristics in Program Operation

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1828
Author(s):  
Jae-Min Sim ◽  
Bong-Seok Kim ◽  
In-Ho Nam ◽  
Yun-Heub Song
Keyword(s):  
Flash Memory ◽  
The Self ◽  
Memory Structure ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Back Gate ◽  
Reliability Characteristics ◽  
Channel Potential ◽  
Stacking Structure

A gate all around with back-gate (GAAB) structure was proposed for 3D NAND Flash memory technology. We demonstrated the excellent characteristics of the GAAB NAND structure, especially in the self-boosting operation. Channel potential of GAAB shows a gradual slope compared with a conventional GAA NAND structure, which leads to excellent reliability characteristics in program disturbance, pass disturbance and oxide break down issue. As a result, the GAAB structure is expected to be appropriate for a high stacking structure of future memory structure.

scholarly journals Investigation of Inhibited Channel Potential of 3D NAND Flash Memory According to Word-Line Location

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 268
Author(s):  
Sangwoo Han ◽  
Youngseok Jeong ◽  
Heesauk Jhon ◽  
Myounggon Kang
Keyword(s):  
Flash Memory ◽  
High Potential ◽  
Potential Difference ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Main Cell ◽  
Channel Potential ◽  
Symmetrical Potential

Natural local self-boosting (NLSB) was analyzed according to the location of a selected word-line (WL) where potential boosting occurs. When the same pattern occurred, it was found that the top cells (WL11 through WL15) and bottom cells (WL0 through WL4) have identically symmetrical potential boosting. In addition, in the region of the middle cells (WL6 through WL10), a slight change in the potential boosting was also almost the same. In the 3D NAND, where there was a dummy WL (DWL), the NLSB for the edge WL changed as the pattern of the DWL changed. The DWL did not affect the NLSB of the main cell, regardless of the pattern. Therefore, the high potential of the edge WL could reduce the potential difference between the main cell and the edge WL using the DWL.

New Read Schemes Using Boosted Channel Potential of Adjacent Bit-Line Strings in nand Flash Memory

2012 ◽  
Vol 33 (8) ◽  
pp. 1198-1200 ◽  
Author(s):  
Sung-Min Joe ◽  
Min-Kyu Jeong ◽  
Myounggon Kang ◽  
Kyoung-Rok Han ◽  
Sung-Kye Park ◽  
...  
Keyword(s):  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Channel Potential

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

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