scholarly journals Analysis of Single Event Effects on Embedded Processor

Electronics ◽  
2021 ◽  
Vol 10 (24) ◽  
pp. 3160
Author(s):  
Sarah Azimi ◽  
Corrado De Sio ◽  
Daniele Rizzieri ◽  
Luca Sterpone
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Fault Models ◽  
Single Event ◽  
Embedded Processor ◽  
Single Event Effects ◽  
Software Application ◽  
Software Applications ◽  
Radiation Induced ◽  
The Impact

The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.

Radiation-Induced Single-Event Effects on the Van Allen Probes Spacecraft

2017 ◽  
Vol 64 (11) ◽  
pp. 2782-2793 ◽  
Author(s):  
Richard H. Maurer ◽  
Kristin Fretz ◽  
Matthew P. Angert ◽  
David L. Bort ◽  
John O. Goldsten ◽  
...  
Keyword(s):  
Single Event ◽  
Single Event Effects ◽  
Van Allen Probes ◽  
Radiation Induced

Analyzing the Robustness of HPC Applications Using a Fine-Grained Soft Error Fault Injection Tool

2016 ◽  
pp. 277-305
Author(s):  
Qiang Guan ◽  
Nathan DeBardeleben ◽  
Sean Blanchard ◽  
Song Fu ◽  
Claude H. Davis IV ◽  
...  
Keyword(s):  
High Performance ◽  
Fault Injection ◽  
Soft Errors ◽  
Small Degree ◽  
Soft Error ◽  
Power Efficient ◽  
Fine Grained ◽  
Different Characteristics ◽  
The Impact ◽  
Performance Computing

As the high performance computing (HPC) community continues to push towards exascale computing, HPC applications of today are only affected by soft errors to a small degree but we expect that this will become a more serious issue as HPC systems grow. We propose F-SEFI, a Fine-grained Soft Error Fault Injector, as a tool for profiling software robustness against soft errors. We utilize soft error injection to mimic the impact of errors on logic circuit behavior. Leveraging the open source virtual machine hypervisor QEMU, F-SEFI enables users to modify emulated machine instructions to introduce soft errors. F-SEFI can control what application, which sub-function, when and how to inject soft errors with different granularities, without interference to other applications that share the same environment. We demonstrate use cases of F-SEFI on several benchmark applications with different characteristics to show how data corruption can propagate to incorrect results. The findings from the fault injection campaign can be used for designing robust software and power-efficient hardware.

Appropriation Infrastructure

2012 ◽  
pp. 254-278 ◽  
Author(s):  
Gunnar Stevens ◽  
Volkmar Pipek ◽  
Volker Wulf
Keyword(s):  
Social Construction ◽  
Design Process ◽  
End User ◽  
Communication Infrastructure ◽  
Software Application ◽  
Empirical Results ◽  
Software Applications ◽  
The Social ◽  
The Impact ◽  
Technological Flexibility

End User Development offers technological flexibility to encourage the appropriation of software applications within specific contexts of use. Appropriation needs to be understood as a phenomenon of many collaborative and creative activities. To support appropriation, we propose integrating communication infrastructure into software application that follows an“easy-to-collaborate”-principle. Such an appropriation infrastructure stimulates the experience sharing among a heterogeneous product community and supports the situated development of usages. Taking the case of the BSCWeasel groupware, we demonstrate how an appropriation infrastructure can be realized. Empirical results from the BSCWeasel project demonstrate the impact of such an infrastructure on the appropriation and design process. Based on these results, we argue that the social construction of IT artifacts should be tightly integrated in the material construction of IT artifacts in bridging design and use discourses.

scholarly journals Radiation-Induced Dose and Single Event Effects in Digital CMOS Image Sensors

2014 ◽  
Vol 61 (6) ◽  
pp. 3331-3340 ◽  
Author(s):  
Cedric Virmontois ◽  
Arthur Toulemont ◽  
Guy Rolland ◽  
Alex Materne ◽  
Valerian Lalucaa ◽  
...  
Keyword(s):  
Image Sensors ◽  
Single Event ◽  
Digital Cmos ◽  
Single Event Effects ◽  
Cmos Image Sensors ◽  
Radiation Induced

Diagnose of radiation induced single event effects in a PLL using a heavy ion microbeam

2013 ◽  
Author(s):  
Santiago Sondon ◽  
Alfredo Falcon ◽  
Pablo Mandolesi ◽  
Pedro Julian ◽  
Nahuel Vega ◽  
...  
Keyword(s):  
Heavy Ion ◽  
Single Event ◽  
Single Event Effects ◽  
Radiation Induced

scholarly journals Fault-Tolerant FPGA-Based Nanosatellite Balancing High-Performance and Safety for Cryptography Application

Electronics ◽  
2021 ◽  
Vol 10 (17) ◽  
pp. 2148
Author(s):  
Laurent Gantel ◽  
Quentin Berthet ◽  
Emna Amri ◽  
Alexandre Karlov ◽  
Andres Upegui
Keyword(s):  
High Performance ◽  
Fault Tolerant ◽  
Fault Injection ◽  
Detection Mechanism ◽  
Radiation Level ◽  
Dynamically Reconfigurable ◽  
Reconfigurable Platform ◽  
Commercial Off The Shelf ◽  
Modular Redundancy ◽  
The Impact

With the growth of the nano-satellites market, the usage of commercial off-the-shelf FPGAs for payload applications is also increasing. Due to the fact that these commercial devices are not radiation-tolerant, it is necessary to enhance them with fault mitigation mechanisms against Single Event Upsets (SEU). Several mechanisms such as memory scrubbing, triple modular redundancy (TMR) and Dynamic and Partial Reconfiguration (DPR), can help to detect, isolate and recover from SEU faults. In this paper, we introduce a dynamically reconfigurable platform equipped with configuration memory scrubbing and TMR mechanisms. We study their impacts when combined with DPR, providing three different execution modes: low-power, safe and high-performance mode. The fault detection mechanism permits the system to measure the radiation level and to estimate the risk of future faults. This enables the possibility of dynamically selecting the appropriate execution mode in order to adopt the best trade-off between performance and reliability. The relevance of the platform is demonstrated in a nano-satellite cryptographic application running on a Zynq UltraScale+ MPSoC device. A fault injection campaign has been performed to evaluate the impact of faulty configuration bits and to assess the efficiency of the proposed mitigation and the overall system reliability.

scholarly journals SimpliFI: Hardware Simulation of Embedded Software Fault Attacks

Cryptography ◽  
2021 ◽  
Vol 5 (2) ◽  
pp. 15
Author(s):  
Jacob Grycel ◽  
Patrick Schaumont
Keyword(s):  
Fault Injection ◽  
Embedded Software ◽  
Fault Models ◽  
Simulation Framework ◽  
Embedded Processor ◽  
Fault Attacks ◽  
Simulation Methodology ◽  
Fault Behavior ◽  
Injection Simulation ◽  
High Level

Fault injection simulation on embedded software is typically captured using a high-level fault model that expresses fault behavior in terms of programmer-observable quantities. These fault models hide the true sensitivity of the underlying processor hardware to fault injection, and they are unable to correctly capture fault effects in the programmer-invisible part of the processor microarchitecture. We present SimpliFI, a simulation methodology to test fault attacks on embedded software using a hardware simulation of the processor running the software. We explain the purpose and advantage of SimpliFI, describe automation of the simulation framework, and apply SimpliFI on a BRISC-V embedded processor running an AES application.

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