Simulating the Influence of Mobile Ionic Oxide Charge on SiC MOS Bias-Temperature Instability Measurements

2015 ◽  
Vol 821-823 ◽  
pp. 697-700 ◽  
Author(s):  
Daniel B. Habersat ◽  
Neil Goldsman ◽  
Aivars J. Lelis
Keyword(s):  
Threshold Voltage ◽  
Drift Diffusion Model ◽  
Drift Diffusion ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Mos Devices ◽  
The Impact ◽  
Ion Species ◽  
Ionic Oxide ◽  
Mos Device

We report here on results obtained using a time-dependent drift-diffusion model to simulate ion transport in the gate oxide of a SiC MOS device during bias-temperature instability measurements to assess the impact on threshold voltage under typical testing conditions. Measured threshold voltage is found to depend strongly on the temperature and mobile ion species, which in combination with the measurement parameters determine how the ions react to the stress and measurement sequence. Simulations show that, based on their mobilities, both potassium-like and copper-like ions may be responsible for experimental observations of a negative trend in threshold instability above 100 °C for SiC MOS devices.

scholarly journals On the Prediction of the Threshold Voltage Degradation in CMOS Technology Due to Bias-Temperature Instability

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 427 ◽  
Author(s):  
Alejandro Campos-Cruz ◽  
Guillermo Espinosa-Flores-Verdad ◽  
Alfonso Torres-Jacome ◽  
Esteban Tlelo-Cuautle
Keyword(s):  
Threshold Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Lookup Table ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
Mos Devices ◽  
Voltage Degradation ◽  
Threshold Voltage Degradation

Currently, researchers face new challenges in order to compensate or even reduce the noxious phenomenon known as bias-temperature instability (BTI) that is present in modern metal-oxide-semiconductor (MOS) technologies, which negatively impacts the performance of semiconductor devices. BTI remains a mystery in the way that it evolves in time, as well as the responsible mechanisms for its appearance and the further degradation it produces on MOS devices. The BTI phenomenon is usually associated with an increase of MOS transistor’s threshold voltage; however, this work also addresses BTI as a change in MOSFET’s drain current, transconductance, and the channel’s resistivity. In this way, we detail a physics-based model to get a better insight into the prediction of threshold voltage degradation for aging ranges going from days to years, in 180-nm MOS technology. We highlight that a physics-based BTI model improves accuracy in comparison to lookup table models. Finally, simulation results for the inclusion of such a physics-based BTI model into BSIM3v3 are shown in order to get a better understanding of how BTI impacts the performance of MOS devices.

scholarly journals Threshold Voltage Degradation for n-Channel 4H-SiC Power MOSFETs

2020 ◽  
Vol 10 (1) ◽  
pp. 3
Author(s):  
Esteban Guevara ◽  
Victor Herrera-Pérez ◽  
Cristian Rocha ◽  
Katherine Guerrero
Keyword(s):  
Silicon Carbide ◽  
Threshold Voltage ◽  
Measurement Data ◽  
Oxide Semiconductor ◽  
Damage Effect ◽  
Temperature Instability ◽  
Characterization Methods ◽  
Power Mosfets ◽  
Bias Temperature Instability ◽  
The Impact

In this study, threshold voltage instability on commercial silicon carbide (SiC) power metal oxide semiconductor field electric transistor MOSFETs was evaluated using devices manufactured from two different manufacturers. The characterization process included PBTI (positive bias temperature instability) and pulsed IV measurements of devices to determine electrical parameters’ degradations. This work proposes an experimental procedure to characterize silicon carbide (SiC) power MOSFETs following two characterization methods: (1) Using the one spot drop down (OSDD) measurement technique to assess the threshold voltage explains temperature dependence when used on devices while they are subjected to high temperatures and different gate voltage stresses. (2) Measurement data processing to obtain hysteresis characteristics variation and the damage effect over threshold voltage. Finally, based on the results, it was concluded that trapping charge does not cause damage on commercial devices due to reduced value of recovery voltage, when a negative small voltage is applied over a long stress time. The motivation of this research was to estimate the impact and importance of the bias temperature instability for the application fields of SiC power n-MOSFETs. The importance of this study lies in the identification of the aforementioned behavior where SiC power n-MOSFETs work together with complementary MOS (CMOS) circuits.

NEGATIVE BIAS TEMPERATURE INSTABILITY IN TIN/HF-SILICATE BASED GATE STACKS

2007 ◽  
Vol 17 (01) ◽  
pp. 129-141
Author(s):  
N. A. CHOWDHURY ◽  
D. MISRA ◽  
N. RAHIM
Keyword(s):  
Interface State ◽  
Initial Time ◽  
Negative Bias ◽  
Gate Stacks ◽  
Negative Bias Temperature Instability ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Bias Temperature Instability ◽  
High Bias ◽  
The Impact

This work studies the effects of negative bias temperature instability (NBTI) on p-channel MOSFETS with TiN/HfSi x O y (20% SiO 2 based high-κ gate stacks under different gate bias and elevated temperature conditions. For low bias conditions, threshold voltage shift (ΔVT) is most probably due to the mixed degradation within the bulk high-κ. For moderately high bias conditions, H-species dissociation in the presence of holes and subsequent diffusion may be initially responsible for interface state and positively charged bulk trap generation. Initial time, temperature and oxide electric field dependence of ΔVT in our devices shows an excellent match with that of SiO 2 based devices, which is explained by reaction-diffusion (R-D) model of NBTI. Under high bias condition at elevated temperatures, due to higher Si - H bond-annealing/bond-breaking ratio, the experimentally observed absence of the impact ionization induced hot holes at the interfacial layer (IL)/ Si interface probably limits the interface state generation and ΔVT as they quickly reach saturation.

Novel Method for Evaluation of Negative Bias Temperature Instability of SiC MOSFETs

2019 ◽  
Vol 963 ◽  
pp. 749-752
Author(s):  
Jose Ortiz Gonzalez ◽  
Olayiwola Alatise ◽  
Philip A. Mawby
Keyword(s):  
Threshold Voltage ◽  
High Reliability ◽  
Gate Oxide ◽  
Gate Bias ◽  
Power Devices ◽  
Threshold Voltage Shift ◽  
Temperature Instability ◽  
Power Semiconductor ◽  
Bias Temperature Instability ◽  
Novel Method

The material properties of SiC make SiC power devices a superior alternative to the conventional Si power devices. However, the reliability of the gate oxide has been a major concern, limiting the adoption of SiC power MOSFETs as the power semiconductor of choice in applications which demand a high reliability. The threshold voltage (VTH) shift caused by Bias Temperature Instability (BTI) has focused the attention of different researchers, with multiple publications on this topic. This paper presents a novel method for evaluating the threshold voltage shift due to negative gate bias and its recovery when the gate bias stress is removed. This method could enable gate oxide reliability assessment techniques and contribute to new qualification methods.

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

2016 ◽  
Vol 4 (1) ◽  
pp. 01-05
Author(s):  
S Suvarna ◽  
K Rajesh ◽  
T Radhu
Keyword(s):  
Threshold Voltage ◽  
High Speed ◽  
Negative Bias ◽  
Positive Bias ◽  
Negative Bias Temperature Instability ◽  
Discrete Cosine Transforms ◽  
Temperature Instability ◽  
Booth Multiplier ◽  
Bias Temperature Instability ◽  
Digital Multipliers

High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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