scholarly journals Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1458 ◽  
Author(s):  
Young Sik Lee ◽  
SoYoung Kim ◽  
Tae Hee Han
Keyword(s):  
Genetic Algorithm ◽  
Network Connectivity ◽  
Aging Effect ◽  
Network On Chip ◽  
Carrier Injection ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Nanoscale System ◽  
Average Latency ◽  
On Chip

As semiconductor processes enter the nanoscale, system-on-chip (SoC) interconnects suffer from link aging owing to negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration. In network-on-chip (NoC) for heterogeneous manycore systems, there is a difference in the aging speed of links depending on the location and utilization of resources. In this paper, we propose a heterogeneous manycore NoC topology synthesis that predicts the aging effect of each link and deploys routers and error correction code (ECC) logic. Aging-aware ECC logic is added to each link to achieve the same link lifetime with less area and latency than the Bose-Chaudhuri-Hocquenghem (BCH) logic. Moreover, based on the modified genetic algorithm, we search for a solution that minimizes the average latency while ensuring the link lifetime by changing the number of routers, location, and network connectivity. Simulation results demonstrate that the aging-aware topology synthesis reduces the average latency of the network by up to 26.68% compared with the aging analysis and the addition of ECC logic on the link after the topology synthesis. Furthermore, topology synthesis with aging-aware ECC logic reduces the maximum average latency by up to 39.49% compared with added BCH logic.

A Novel Adaptive Routing Algorithm for Network-On-Chip

2011 ◽  
Vol 474-476 ◽  
pp. 413-416
Author(s):  
Jia Jia ◽  
Duan Zhou ◽  
Jian Xian Zhang
Keyword(s):  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Experimental Results ◽  
Average Latency ◽  
On Chip

In this paper, we propose a novel adaptive routing algorithm to solve the communication congestion problem for Network-on-Chip (NoC). The strategy competing for output ports in both X and Y directions is employed to utilize the output ports of the router sufficiently, and to reduce the transmission latency and improve the throughput. Experimental results show that the proposed algorithm is very effective in relieving the communication congestion, and a reduction in average latency by 45.7% and an improvement in throughput by 44.4% are achieved compared with the deterministic XY routing algorithm and the simple XY adaptive routing algorithm.

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

2009 ◽  
Vol 17 (5) ◽  
pp. 674-687 ◽  
Author(s):  
G. Leary ◽  
K. Srinivasan ◽  
K. Mehta ◽  
K.S. Chatha
Keyword(s):  
Genetic Algorithm ◽  
Network On Chip ◽  
On Chip

scholarly journals Genetic algorithm for task mapping in embedded systems on a hierarchical architecture based on wireless network on chip WiNoC

DYNA ◽  
2017 ◽  
Vol 84 (201) ◽  
pp. 202 ◽  
Author(s):  
Maribell Sacanamboy Franco ◽  
Freddy Bolaños-Martinez ◽  
Álvaro Bernal-Noreña ◽  
Rubén Nieto-Londoño
Keyword(s):  
Genetic Algorithm ◽  
Embedded Systems ◽  
Wireless Network ◽  
Network On Chip ◽  
Hierarchical Architecture ◽  
Task Mapping ◽  
On Chip ◽  
La Red

Los sistemas de red en chip (NoC) fueron desarrollados originalmente para proporcionar un alto rendimiento, mediante la disponibilidad de varias unidades de procesamiento, conectadas a través de una red cableada dentro del circuito integrado. Wireless NoC (WiNoC o WNoC) son una evolución natural de los sistemas NoC, que integran una comunicación jerárquica dentro del chip para mejorar la escalabilidad. El mapeo de tareas en los sistemas WNoC representa un proceso desafiante, que a menudo implica varios objetivos de optimización, como potencia, rendimiento, productividad, uso de recursos y métricas de red. Este artículo describe un algoritmo genético basado en un enfoque para encontrar soluciones óptimas de asignación de tareas en tiempo de diseño, para sistemas embebidos que trabajan sobre un WiNoC. Los objetivos de optimización fueron: Aceleración, Consumo de Energía y Ancho de Banda. La red de destino utilizada para la simulación puede ser vista como un WiNoC jerárquica de dos niveles. El primer nivel corresponde a un conjunto de subredes que están conectadas por cables y son de tipo malla. El segundo nivel corresponde a una topología en estrella de enlaces inalámbricos, que conectan las subredes de primer nivel. El algoritmo propuesto muestra un buen desempeño en relación con los objetivos de optimización y la WiNoC heterogéneo simulada.

scholarly journals Network-on-Chip Irregular Topology Optimization for Real-Time and Non-Real-Time Applications

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1196
Author(s):  
Samuel da Silva Oliveira ◽  
Bruno Motta de Carvalho ◽  
Márcio Eduardo Kreutz
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Network On Chip ◽  
Chip Area ◽  
Average Latency ◽  
Real Time Applications ◽  
On Chip

Network-on-Chip is a good approach to working on intra-chip communication. Networks with irregular topologies may be better suited for specific applications because of their architectural nature. A good design space exploration can help the design of the network to obtain more optimized topologies. This paper proposes a way of optimizing networks with irregular topologies through the use of a genetic algorithm. The network proposed here has heterogeneous routers that aim to optimize the network and support applications with real-time tasks. The goal is to find networks that are optimized for average latency and percentage of real-time packets delivered within the deadline. The results show that we have been able to find networks that can deliver all the real-time packets, obtain acceptable latency values, and shrink the chip area.

scholarly journals 3.3V Transmitter Using 1.8V Transistors In A Cascode Configuration

2021 ◽  
Author(s):  
Marcs Ng
Keyword(s):  
Integrated Circuits ◽  
Transmission Rate ◽  
Carrier Injection ◽  
Digital Integrated Circuits ◽  
Negative Bias Temperature Instability ◽  
Hot Carrier ◽  
Bias Temperature Instability ◽  
Hot Carrier Injection ◽  
Capacitive Load ◽  
Ac Transmission

A voltage-mode transmitter using a 1.8V-to-3.3V levelshifter and cascoded output buffer is proposed. 1.8V TSMC 65nm transistors are used. The design is targeted to meet JEDEC Interface Standard for Nominal 3 V/3.3 V Supply Digital Integrated Circuits DC Specifications as well as an AC transmission rate of 200 MHz on a 30 cm 50Ω board trace terminated with a 4 pF capacitive load. Overstress voltages will not be exceeded in order to avoid device failure due to breaching Gate Oxide Integrity, Hot Carrier Injection, or Negative Bias Temperature Instability.

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