hierarchical architecture
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Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8217
Author(s):  
Oliver W. Layton

Most algorithms for steering, obstacle avoidance, and moving object detection rely on accurate self-motion estimation, a problem animals solve in real time as they navigate through diverse environments. One biological solution leverages optic flow, the changing pattern of motion experienced on the eye during self-motion. Here I present ARTFLOW, a biologically inspired neural network that learns patterns in optic flow to encode the observer’s self-motion. The network combines the fuzzy ART unsupervised learning algorithm with a hierarchical architecture based on the primate visual system. This design affords fast, local feature learning across parallel modules in each network layer. Simulations show that the network is capable of learning stable patterns from optic flow simulating self-motion through environments of varying complexity with only one epoch of training. ARTFLOW trains substantially faster and yields self-motion estimates that are far more accurate than a comparable network that relies on Hebbian learning. I show how ARTFLOW serves as a generative model to predict the optic flow that corresponds to neural activations distributed across the network.


Energies ◽  
2021 ◽  
Vol 14 (23) ◽  
pp. 8171
Author(s):  
Asfandyar Khan ◽  
Arif Iqbal Umar ◽  
Arslan Munir ◽  
Syed Hamad Shirazi ◽  
Muazzam A. Khan ◽  
...  

The Internet of things (IoT) enables a diverse set of applications such as distribution automation, smart cities, wireless sensor networks, and advanced metering infrastructure (AMI). In smart grids (SGs), quality of service (QoS) and AMI traffic management need to be considered in the design of efficient AMI architectures. In this article, we propose a QoS-aware machine-learning-based framework for AMI applications in smart grids. Our proposed framework comprises a three-tier hierarchical architecture for AMI applications, a machine-learning-based hierarchical clustering approach, and a priority-based scheduling technique to ensure QoS in AMI applications in smart grids. We introduce a three-tier hierarchical architecture for AMI applications in smart grids to take advantage of IoT communication technologies and the cloud infrastructure. In this architecture, smart meters are deployed over a georeferenced area where the control center has remote access over the Internet to these network devices. More specifically, these devices can be digitally controlled and monitored using simple web interfaces such as REST APIs. We modify the existing K-means algorithm to construct a hierarchical clustering topology that employs Wi-SUN technology for bi-directional communication between smart meters and data concentrators. Further, we develop a queuing model in which different priorities are assigned to each item of the critical and normal AMI traffic based on its latency and packet size. The critical AMI traffic is scheduled first using priority-based scheduling while the normal traffic is scheduled with a first-in–first-out scheduling scheme to ensure the QoS requirements of both traffic classes in the smart grid network. The numerical results demonstrate that the target coverage and connectivity requirements of all smart meters are fulfilled with the least number of data concentrators in the design. Additionally, the numerical results show that the architectural cost is reduced, and the bottleneck problem of the data concentrator is eliminated. Furthermore, the performance of the proposed framework is evaluated and validated on the CloudSim simulator. The simulation results of our proposed framework show efficient performance in terms of CPU utilization compared to a traditional framework that uses single-hop communication from smart meters to data concentrators with a first-in–first-out scheduling scheme.


2021 ◽  
Author(s):  
Kai Yuan ◽  
Noor Sajid ◽  
Karl Friston ◽  
Zhibin Li

Abstract Humans can produce complex movements when interacting with their surroundings. This relies on the planning of various movements and subsequent execution. In this paper, we investigated this fundamental aspect of motor control in the setting of autonomous robotic operations. We consider hierarchical generative modelling—for autonomous task completion—that mimics the deep temporal architecture of human motor control. Here, temporal depth refers to the nested time scales at which successive levels of a forward or generative model unfold: for example, the apprehension and delivery of an object requires both a global plan that contextualises the fast coordination of multiple local limb movements. This separation of temporal scales can also be motivated from a robotics and control perspective. Specifically, to ensure versatile sensorimotor control, it is necessary to hierarchically structure high-level planning and low-level motor control of individual limbs. We use numerical experiments to establish the efficacy of this formulation and demonstrate how a humanoid robot can autonomously solve a complex task requiring locomotion, manipulation, and grasping, using a hierarchical generative model. In particular, the humanoid robot can retrieve and deliver a box, open and walk through a door to reach the final destination. Our approach, and experiments, illustrate the effectiveness of using human-inspired motor control algorithms, which provide a scalable hierarchical architecture for autonomous performance of complex goal-directed tasks.


2021 ◽  
Author(s):  
Haibin Sun ◽  
Shuang-Shuang Liang ◽  
Zijun Xu ◽  
Wenrui Zheng ◽  
Xiaoyu Liu ◽  
...  

Abstract We successfully designed and prepared hierarchical Ni3S2 nanosheet@nanorod arrays on three-dimensional Ni foam via facile hydrothermal sulfuration. We conducted a series of time- and temperature-dependent experiments to determine the Ostwald ripening process of hierarchical Ni3S2 nanosheet@nanorod arrays. The rationally hierarchical architecture creates an excellent supercapacitor electrode for Ni3S2 nanosheet@nanorod arrays. The areal capacitance of this array reaches 5.5 F cm-2 at 2 mA cm-2, which is much higher than that of Ni3S2 nanosheet arrays (1.5 F cm-2). The corresponding asymmetric supercapacitor exhibits a wide potential window of 1.6 V and energy density up to 1.0 Wh cm-2 when the proposed array is utilized as the positive electrode with activated carbon as the negative electrode. This electrochemical performance enhancement is attributable to the hierarchical structure and synergistic cooperation of macroporous Ni foam and well-aligned Ni3S2 nanosheet@nanorod arrays. Our results represent a promising approach to the preparation of hierarchical nanosheet@nanorod arrays as high-performing electrochemical capacitors.


Author(s):  
Lu Chen ◽  
Wenjing Deng ◽  
Zhi Chen ◽  
Xiaolei Wang

Abstract An effective technique for improving electrochemical efficiency is to rationally design hierarchical nanostructures that completely optimize the advantages of single components and establish an interfacial effect between structures. In this study, core–shell NiMoO4@Ni9S8/MoS2 hetero-structured nanorods are prepared via a facile hydrothermal process followed by a direct sulfurization. The resulting hierarchical architecture with outer Ni9S8/MoS2 nanoflakes shell on the inner NiMoO4 core offers plentiful active sites and ample charge transfer pathways in continuous heterointerfaces. Ascribing to the porous core–shell configuration and synergistic effect of bimetal sulfides, the obtained NiMoO4@Ni9S8/MoS2 as electrode material presents an unsurpassed specific capacity of 373.4 F g−1 at 10 A g−1 and remarkable cycling performance in the 6 M KOH electrolyte. This work delivers a rational method for designing highly efficient electrodes for supercapacitors, enlightening the road of exploring low-cost materials in the energy storage domain. Graphical Abstract


2021 ◽  
Vol 2083 (2) ◽  
pp. 022032
Author(s):  
Yongzheng Zhan ◽  
Tuo Li ◽  
Yuqiu Yue ◽  
Tongqiang Liu ◽  
Yulong Zhou ◽  
...  

Abstract A lower power 25Gb/s 16:1 multiplexer using 65nm CMOS technology for 400Gb/s Ethernet (400GbE) physical layer (PHY) interface was presented. CMOS+CML mixed logic is adopted to achieve hierarchical architecture, avoiding the high clock requirement of one-step structure and improving the transmission speed. In order to reduce power while achieving high data rate, multiplexing structure is also optimized by utilizing multi-frequency multi-phase technology which not only ensures the requirement of the phase stabilization, but also leaves out some flip-flops. For CMOS-CML conversion circuit, transmission gate and cross-coupled CMOS inverter are used to match the delay of CMOS inverter, suppressing the effect of common-mode noise. Simulation results show that the multiplexer works correctly and jitter of output signal is less than 0.1UI. When voltage is 1.2V, the total power is 32.7mW at 25Gb/s.


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