scholarly journals Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating Applications

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1406
Author(s):  
Jaeyoung Park
Keyword(s):  
Tunnel Junction ◽  
Magnetic Tunnel Junction ◽  
Low Energy ◽  
The Other ◽  
Energy Reduction ◽  
Power Gating ◽  
Spin Orbit ◽  
Flip Flop ◽  
Area Overhead ◽  
Nmos Transistors

This paper presents two novel hybrid non-volatile flip-flops (NVFFs) comprised of the conventional CMOS flip-flop for static storage in normal operations and Spin-Orbit-Torque Magnetic Tunnel Junction (SOT-MTJ) devices for temporary storage during power gating. The proposed NVFFs re-utilize a part of the standard CMOS flip-flop infrastructure for storing and restoring data onto MTJs for reducing the area. Furthermore, the proposed NVFFs re-use a write current, which is used for storing an MTJ, to write the other MTJ at a time, resulting in 50% storing energy reduction. To reduce the area further, the number of external terminals of an MTJ is reduced by shorting the shorting physical terminals. Removing a terminal using the proposed STT-Like SOT configuration results in fewer transistors to control. The proposed NVFF circuits are evaluated using a compact MTJ model targeting implementation in a 14-nm technology node. Analysis indicates that area overheads are only 10.3% and 6.9% compared to the conventional D flip-flop because three or two minimum-sized NMOS transistors are added for accessing MTJs. Compared to the best previously known NVFFs, the proposed NVFF has an improvement by a factor of 2–8 in terms of the area overhead.

scholarly journals Domain wall-magnetic tunnel junction spin–orbit torque devices and circuits for in-memory computing

2021 ◽  
Vol 118 (11) ◽  
pp. 112401
Author(s):  
Mahshid Alamdar ◽  
Thomas Leonard ◽  
Can Cui ◽  
Bishweshwor P. Rimal ◽  
Lin Xue ◽  
...  
Keyword(s):  
Domain Wall ◽  
Tunnel Junction ◽  
Magnetic Tunnel Junction ◽  
Spin Orbit

scholarly journals Voltage Controlled Domain Wall Motion based Neuron and Stochastic Magnetic Tunnel Junction Synapse for Neuromorphic Computing Applications

2021 ◽  
Author(s):  
Aijaz Lone ◽  
Selma Amara ◽  
Hossein Fariborzi
Keyword(s):  
Domain Wall ◽  
Tunnel Junction ◽  
Thermal Noise ◽  
Wall Motion ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Spin Orbit ◽  
Free Layer ◽  
Digit Recognition ◽  
Transport Studies

The present work discusses the proposal of a spintronic neuromorphic system with spin orbit torque driven domain wall motion-based neuron and synapse. We propose a voltage-controlled magnetic anisotropy domain wall motion based magnetic tunnel junction neuron. We investigate how the electric field at the gate (pinning site), generated by the voltage signals from pre-neurons, modulates the domain wall motion, which reflects in the non-linear switching behaviour of neuron magnetization. For the implementation of synaptic weights, we propose 3-terminal MTJ with stochastic domain wall motion in the free layer. We incorporate intrinsic pinning effects by creating triangular notches on the sides of the free layer. The pinning of domain wall and intrinsic thermal noise of device lead to the stochastic behaviour of domain wall motion. The control of this stochasticity by the spin orbit torque is shown to realize the potentiation and depression of the synaptic weight. The micromagnetics and spin transport studies in synapse and neuron are carried out by developing a coupled micromagnetic Non-Equilibrium Green’s Function (<i>MuMag-NEGF</i>) model. The minimization of the writing current pulse width by leveraging the thermal noise and demagnetization energy is also presented. Finally, we discuss the implementation of digit recognition by the proposed system using a spike time dependent algorithm.

scholarly journals Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop

Micromachines ◽  
2019 ◽  
Vol 10 (6) ◽  
pp. 411 ◽  
Author(s):  
Jaeyoung Park ◽  
Young Yim
Keyword(s):  
Field Effect Transistor ◽  
Magnetic Tunnel Junction ◽  
Oxide Semiconductor ◽  
Pulse Modulation ◽  
Flip Flop ◽  
Fine Grained ◽  
Temporary Storage ◽  
Area Overhead ◽  
Effect Transistor ◽  
A Current

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is 6.9 % normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by 4.1 × and the energy by 1.5 × . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

scholarly journals Anomalous and spin Hall effects in a magnetic tunnel junction with Rashba spin-orbit coupling

2013 ◽  
Vol 103 (3) ◽  
pp. 032406 ◽  
Author(s):  
A. V. Vedyayev ◽  
M. S. Titova ◽  
N. V. Ryzhanova ◽  
M. Ye. Zhuravlev ◽  
E. Y. Tsymbal
Keyword(s):  
Tunnel Junction ◽  
Magnetic Tunnel Junction ◽  
Orbit Coupling ◽  
Spin Orbit Coupling ◽  
Spin Orbit ◽  
Rashba Spin ◽  
Hall Effects ◽  
Spin Hall Effects
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