scholarly journals RISC Conversions for LNS Arithmetic in Embedded Systems

Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1208 ◽  
Author(s):  
Peter Drahoš ◽  
Michal Kocúr ◽  
Oto Haffner ◽  
Erik Kučera ◽  
Alena Kozáková
Keyword(s):  
Embedded Systems ◽  
Number System ◽  
Real Time Control ◽  
Gate Arrays ◽  
Time Control ◽  
Camera Systems ◽  
Control Units ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Logarithmic Number

The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC). The core of the proposed method is a newly developed algorithm for conversion between LNS and the floating point (FLP) representations named “looping in sectors”, which brings about reduced memory consumption without a loss of accuracy. The resulting effective RISC conversions use only elementary computer operations without the need to employ multiplication, division, or other functions. Verification of the new concept and related developed algorithms for conversion between the LNS and the FLP representations was realized on Field Programmable Gate Arrays (FPGA), and the conversion accuracy was evaluated via simulation. Using the proposed method, a maximum relative conversion error of less than ±0.001% was achieved with a 22-ns delay and a total of 50 slices of FPGA consumed including memory cells. Promising applications of the proposed method are in embedded systems that are expanding into increasingly demanding applications, such as camera systems, lidars and 2D/3D image processing, neural networks, car control units, autonomous control systems that require more computing power, etc. In embedded systems for real-time control, the developed conversion algorithm can appear in two forms: as RISC conversions or as a simple RISC-based logarithmic addition.

Design of EMB-Based Moore FSMs

2017 ◽  
Vol 26 (07) ◽  
pp. 1750125 ◽  
Author(s):  
Małgorzata Kołopieńczyk ◽  
Larysa Titarenko ◽  
Alexander Barkalov
Keyword(s):  
Control Unit ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Complexity Of Algorithms ◽  
Gate Arrays ◽  
Control Units ◽  
Finite State ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Effective Use

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

The IP Design for a Customized Mobile SoC

2012 ◽  
Vol 605-607 ◽  
pp. 2087-2090
Author(s):  
Xiang Wen Liu ◽  
Li Min Liu
Keyword(s):  
Intellectual Property ◽  
Embedded Systems ◽  
Field Programmable Gate Arrays ◽  
Monitor System ◽  
Gate Arrays ◽  
Semiconductor Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
System On A Chip ◽  
Mobile Soc

IP, Intellectual Property, modules are essential and important for SoC applications. SoC, System on a Chip, is a system integrated on a single semiconductor chip. It is a research hot-point in embedded systems. In this paper, the IP design for a customized mobile SoC is discussed. The customized mobile SoC integrates a mobile computing control or monitor system into one chip FPGA, Field Programmable Gate Arrays. The SoC is required smaller in size and more efficient in operation.

scholarly journals Reduction in the number of LUT elements for control units with code sharing

2010 ◽  
Vol 20 (4) ◽  
pp. 751-761 ◽  
Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Jacek Bieganowski
Keyword(s):  
Field Programmable Gate Arrays ◽  
Logic Circuits ◽  
Embedded Memory ◽  
Gate Arrays ◽  
Look Up Table ◽  
Control Units ◽  
Linear Chains ◽  
Code Sharing ◽  
Field Programmable ◽  
Programmable Gate Arrays

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

scholarly journals Implementation of an ARM-based system using a Xilinx ZYNQ SoC

2019 ◽  
Vol 13 (2) ◽  
pp. 485
Author(s):  
Omar Salem Baans ◽  
Asral Bahari Jambek
Keyword(s):  
Embedded Systems ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Software System ◽  
Gate Arrays ◽  
Arm Processor ◽  
Systems On Chip ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

<span>ARM processors are widely used in embedded systems. They are often implemented as microcontrollers, field-programmable gate arrays (FPGAs) or systems-on-chip. In this paper, a variety of ARM processor platform implementations are reviewed, such as implementation into a microcontroller, a system-on-chip and a hybrid ARM-FPGA platform. Furthermore, the implementation of a specific ARM processor, the Cortex-A9 processor, into a system-on-chip (SoC) on an FPGA is discussed using Xilinx’s Vivado and SDK software system and execution on a Xilinx Zynq Board.</span>

scholarly journals Identify a Spoofing Attack on an In-Vehicle CAN Bus Based on the Deep Features of an ECU Fingerprint Signal

Smart Cities ◽  
2020 ◽  
Vol 3 (1) ◽  
pp. 17-30
Author(s):  
Yun Yang ◽  
Zongtao Duan ◽  
Mark Tehranipoor
Keyword(s):  
Autonomous Vehicles ◽  
Short Term Memory ◽  
Can Bus ◽  
Area Network ◽  
Gate Arrays ◽  
Control Units ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Long Short Term Memory ◽  
High Computational Complexity

An in-vehicle controller area network (CAN) bus is vulnerable because of increased sharing among modern autonomous vehicles and the weak protocol design principle. Spoofing attacks on a CAN bus can be difficult to detect and have the potential to enable devastating attacks. To effectively identify spoofing attacks, we propose the authentication of sender identities using a recurrent neural network with long short-term memory units (RNN-LSTM) based on the features of a fingerprint signal. We also present a way to generate the analog fingerprint signals of electronic control units (ECUs) to train the proposed RNN-LSTM classifier. The proposed RNN-LSTM model is accelerated on embedded Field-Programmable Gate Arrays (FPGA) to allow for real-time detection despite high computational complexity. A comparison of experimental results with the latest studies demonstrates the capability of the proposed RNN-LSTM model and its potential as a solution to in-vehicle CAN bus security.

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