scholarly journals A Breakdown Enhanced AlGaN/GaN Schottky Barrier Diode with the T-Anode Position Deep into the Bottom Buffer Layer

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 91 ◽  
Author(s):  
Youlei Sun ◽  
Ying Wang ◽  
Jianxiang Tang ◽  
Wenju Wang ◽  
Yifei Huang ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Buffer Layer ◽  
Computer Aided Design ◽  
Tunneling Current ◽  
Cathode Region ◽  
Schottky Barrier Diode ◽  
Electrical Characteristics ◽  
Edge Termination ◽  
Dimensional Electron Gas ◽  
Aided Design

In this paper, an AlGaN/GaN Schottky barrier diode (SBD) with the T-anode located deep into the bottom buffer layer in combination with field plates (TAI-BBF FPs SBD) is proposed. The electrical characteristics of the proposed structure and the conventional AlGaN/GaN SBD with gated edge termination (GET SBD) were simulated and compared using a Technology Computer Aided Design (TCAD) tool. The results proved that the breakdown voltage (VBK) in the proposed structure was tremendously improved when compared to the GET SBD. This enhancement is attributed to the suppression of the anode tunneling current by the T-anode and the redistribution of the electric field in the anode–cathode region induced by the field plates (FPs). Moreover, the T-anode had a negligible effect on the two-dimensional electron gas (2DEG) in the channel layer, so there is no deterioration in the forward characteristics. After being optimized, the proposed structure exhibited a low turn-on voltage (VT) of 0.53 V and a specific on-resistance (RON,sp) of 0.32 mΩ·cm2, which was similar to the GET SBD. Meanwhile, the TAI-BBF FP SBD with an anode-cathode spacing of 5 μm achieved a VBK of 1252 V, which was enhanced almost six times compared to the GET SBD with a VBK of 213 V.

Electrical characteristics of an organic thin copolymer/p-Si Schottky barrier diode

2010 ◽  
Vol 518 (15) ◽  
pp. 4375-4379 ◽  
Author(s):  
Savaş Sönmezoğlu ◽  
Sevilay Şenkul ◽  
Recep Taş ◽  
Güven Çankaya ◽  
Muzaffer Can
Keyword(s):  
Schottky Barrier ◽  
Schottky Barrier Diode ◽  
Electrical Characteristics

A 1100 + V AlGaN/GaN-Based Planar Schottky Barrier Diode without Edge Termination

2011 ◽  
Vol 28 (1) ◽  
pp. 017303 ◽  
Author(s):  
Dong-Sheng Cao ◽  
Hai Lu ◽  
Dun-Jun Chen ◽  
Ping Han ◽  
Rong Zhang ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Schottky Barrier Diode ◽  
Edge Termination

scholarly journals Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Buffer Layers ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Insulated Gate Bipolar Transistor ◽  
Computer Aided ◽  
Long Time ◽  
Tcad Simulation ◽  
Aided Design

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

scholarly journals Study of a SiC Trench MOSFET Edge-Termination Structure with a Bottom Protection Well for a High Breakdown Voltage

2020 ◽  
Vol 10 (3) ◽  
pp. 753
Author(s):  
Jee-Hun Jeong ◽  
Ju-Hong Cha ◽  
Goon-Ho Kim ◽  
Sung-Hwan Cho ◽  
Ho-Jun Lee
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Surface Region ◽  
Ring Structure ◽  
Oxide Semiconductor ◽  
Cross Sectional ◽  
Edge Termination ◽  
Additional Process ◽  
Aided Design ◽  
Sectional Structure

A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodically depleted surface region formed between a heavily doped equipotential region. On the other hand, in the trenched ring structure, an additional quasi-equipotential region is provided by the BPW region, which enables deeper and wider field-spreading profiles, and less field crowding at the edge region. The two-dimensional Technology Computer Aided Design (2D-TCAD) simulation results show that the proposed trenched ring-edge termination structures have an improved breakdown voltage compared to the conventional floating field ring structure.

Investigation of Package Effects on the Edge Termination E-Field for HV WBG Power Semiconductors

2017 ◽  
Vol 2017 (1) ◽  
pp. 000224-000230
Author(s):  
Haotao Ke ◽  
Yifan Jiang ◽  
Adam J. Morgan ◽  
Douglas C. Hopkins
Keyword(s):  
Schottky Barrier ◽  
Field Distribution ◽  
Schottky Barrier Diode ◽  
Power Device ◽  
Guard Ring ◽  
Power Devices ◽  
Conducting Plane ◽  
Power Semiconductor ◽  
Edge Termination ◽  
Reverse Blocking

Abstract The edge termination of a power semiconductor is defined as the spatial junction terminations around the edges of the power devices. Guard rings are used to contour the internal depletion regions and E-fields as they terminate at the edge termination, i.e. the intersection of the depletion regions and the wafer saw line where the crystal damage is located. Since there is no specific package for WBG power devices, wire bonds are still widely used to interconnect to the topside metal pads of the power devices. From previous research it is shown that wire bonding will not affect the E-field around the guard rings on a WBG device. However, planar power package, such as double-sided and power flip-chip device packaging could be a problem where the close distance between the topside of the power device and conducting plane may negatively affect the E-field distribution of the guard rings, which in turn lowers the reverse blocking capability of the WBG power device and increases leakage current creating greater on-state power loss, or even early break down. Few works have shown the Electric field distribution in embedded power modules. Therefore, a more detailed investigation and possible solution is needed for the proliferation of double-sided power packages. To investigate this packaging problem simulations were performed in Sentaurus TCAD and COMSOL based on the device physics and package geometries. Guard ring structures in 1.2kV and 10kV SiC Schottky Barrier Diode (SBD) were built and simulated in various double-sided package geometries, together with the thermal and mechanical evaluation of the package, to observe the influence on the E-field distribution in and out the WBG device. Different double-sided package structures were evaluated and a guideline (spacing/pad size/etc.) summarized for double-sided design. Moreover, a new bevel edge termination method was evaluated for double-sided WBG power semiconductor devices. Experimental reverse blocking test results will be reported in various temperature (from 25°C to 175°C) to verify the function of the package. The tests are on 1200V/50A SiC SBD (Schottky Barrier Diode) from Global Power Technology, which has double-sided Ag on both sides.

A Simulation Study on Reducing the Grain Boundary Position Dependency in Tunneling Thin-Film Transistors Using a Wide Tunneling Area

2020 ◽  
Vol 20 (11) ◽  
pp. 6627-6631
Author(s):  
Hyun-Min Kim ◽  
Junil Lee ◽  
Yunho Choi ◽  
Jong-Ho Lee ◽  
Byung-Gook Park
Keyword(s):  
Grain Boundary ◽  
Computer Aided Design ◽  
Deposition Process ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Limited Region ◽  
Layer Deposition ◽  
Boundary Position ◽  
Simulation Results ◽  
Aided Design

In this paper, we confirmed the effect of the grain boundary position dependency on short channel poly-Si Tunneling TFTs using technology computer aided design (TCAD) simulation. The simulation results show that the grain boundary (GB) in the channel affects the tunneling barrier and thus, produces variations in the electrical characteristics of the device such as the Vth and off-current. In the case of tunneling TFTs, the characteristics of the entire device are determined by the band to band tunneling (BTBT) currents occurring in very limited regions. In this study, we proposed that a TFT device requires a wider BTBT region because this limited region worsens the variations in the electrical characteristics of the TFT device. Two additional methods were proposed, one using vertical BTBT over a wide area through an additional poly-Si layer deposition and one widening the BTBT area through tilting implantation without an additional deposition process. The simulation results show that the variation of Vth is reduced to 10% through the extension of the BTBT area.

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